AD7834/AD7835

REV. A

–5–

AD7834 PIN DESCRIPTION

Pin Mnemonic

Description

Logic Power Supply; +5 V

± 5%.

Negative Analog Power Supply; –15 V

± 5%.

Positive Analog Power Supply; +15 V

± 5%.

DGND

Digital Ground.

AGND

Analog Ground.

Positive Reference Input. The positive reference voltage is referred to AGND.

Negative Reference Input. The negative reference voltage is referred to AGND.

DAC Outputs.

DSG

Device Sense Ground Input. Used in conjunction with the CLR input for power-on protection of the DACs.

When CLR is low, the DAC outputs are forced to the potential on the DSG pin.

DIN

Serial Data Input.

SCLK

Clock input for writing data to the device.

FSYNC

Frame Sync Input. Active low logic input used, in conjunction with DIN and SCLK, to write data to the device

with serial data expected after the falling edge of this signal. The contents of the 24-bit serial-to-parallel input

register are transferred on the rising edge of this signal.

PA0 . . . PA4

addresses in a multipackage environment.

PAEN

Package Address Enable Input. When low, this input allows normal operation of the device. When it is high, the

device ignores the package address (but not the channel address) in the serial data stream and loads the serial

data into the input registers. This feature is useful in a multipackage application where it can be used to load the

same data into the same channel in each package.

LDAC

Load DAC Input (level sensitive). This input signal in conjunction with the FSYNC input signal, determines

how the analog outputs are updated. If LDAC is maintained high while new data is being loaded into the

device’s input registers, no change occurs on the analog outputs. Subsequently, when LDAC is brought low, the

contents of all four input registers are transferred into their respective DAC latches, updating the analog outputs.

Alternatively, if LDAC is kept low while new data is shifted into the device, then the addressed DAC latch (and

corresponding analog output) is updated immediately on the rising edge of FSYNC.

CLR

Asynchronous Clear Input (level sensitive, active low). When this input is brought low, all analog outputs are

switched to the externally set potential on the DSG pin. When CLR is brought high, the signal outputs remain at

the DSG potential until LDAC is brought low. When LDAC is brought low, the analog outputs are switched

back to reflect their individual DAC output levels. As long as CLR remains low, the LDAC signals are ignored

and the signal outputs remain switched to the potential on the DSG pin.

PIN CONFIGURATION

DIP AND SOIC

14

13

12

11

17

16

15

20

19

18

10

9

8

1

2

3

4

7

6

5

28

27

26

25

24

23

22

21

TOP VIEW

(Not to Scale)

NC = NO CONNECT

NC

NC

NC

AGND

DSG

NC

NC

DGND

SCLK

LDAC

CLR

DIN

PA0

PA1

PA2

FSYNC

PA3

PA4

PAEN

AD7834