AD7835AS datasheet(3/16 Pages) AD

3 / 16 page

AD7834/AD7835

REV. A

–3–

TIMING SPECIFICATIONS1

Parameter

Limit at TMIN, TMAX

Units

Description

AD7834 Specific

100

ns min

SCLK Cycle Time

ns min

SCLK Low Time @ +25

°C

ns min

SCLK Low Time –40

°C to +85°C

ns min

SCLK Low Time –55

°C to +125°C

ns min

SCLK High Time

ns min

FSYNC

, PAEN Setup Time

ns min

FSYNC

, PAEN Hold Time

ns min

Data Setup Time

ns min

Data Hold Time

ns min

LDAC

to FSYNC Setup Time

ns min

LDAC

to FSYNC Hold Time

t21

ns min

Delay Between Write Operations

AD7835 Specific

t11

ns min

A0, A1, A2, BYSHF to CS Setup Time

t12

ns min

A0, A1, A2, BYSHF to CS Hold Time

t13

ns min

to WR Setup Time

t14

ns min

to WR Hold Time

t15

ns min

Pulse Width

t16

ns min

Data Setup Time

t17

ns min

Data Hold Time

t18

ns min

LDAC

to CS Setup Time

t19

ns min

to LDAC Setup Time

t20

ns min

LDAC

to CS Hold Time

General

t10

ns min

LDAC

, CLR Pulse Width

NOTES

1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.

2Rise and fall times should be no longer than 50 ns.

Specifications subject to change without notice.

(VCC = +5 V

± 5%; V

DD = +15 V

± 5%; V

SS = –15 V

± 5%; AGND = DGND = 0 V)

t12

t14

t17

t16

t15

t10

t18

t19

t11

t13

A0. A1 A2

BYSHF

DATA

LDAC

(SIMULTANEOUS

UPDATE)

LDAC

(PRE-CHANNEL

UPDATE)

Figure 2. AD7835 Timing Diagram

t10

t20

LDAC

(SIMULTANEOUS

UPDATE)

LDAC

(PRE-CHANNEL

UPDATE)

1ST

CLK

2ND

CLK

24TH

CLK

D22

D23

SCLK

DIN

FSYNC

Figure 1. AD7834 Timing Diagram

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