AD9883SLASHPCB datasheet(16/24 Pages) AD

16 / 24 page

REV. 0

AD9883

–16–

screen, and a slow recovery from large changes in the

Average Picture Level (APL), or brightness.

When Clamp Function = 1, this register is ignored.

Hsync PULSEWIDTH

7–0

Hsync Output Pulsewidth

An 8-bit register that sets the duration of the Hsync

output pulse.

The leading edge of the Hsync output is triggered by the

internally generated, phase-adjusted PLL feedback clock.

The AD9883 then counts a number of pixel clocks equal

to the value in this register. This triggers the trailing edge

of the Hsync output, which is also phase-adjusted.

INPUT GAIN

7–0

Red Channel Gain Adjust

An 8-bit word that sets the gain of the RED channel.

The AD9883 can accommodate input signals with a

full-scale range of between 0.5 V and 1.5 V p-p. Setting

REDGAIN to 255 corresponds to an input range of

1.0 V. A REDGAIN of 0 establishes an input range of

0.5 V. Note that INCREASING REDGAIN results in the

picture having LESS CONTRAST (the input signal

uses fewer of the available converter codes). See Figure 2.

7–0

Green Channel Gain Adjust

An 8-bit word that sets the gain of the GREEN channel.

See REDGAIN (08).

7–0

Blue Channel Gain Adjust

An 8-bit word that sets the gain of the BLUE channel.

See REDGAIN (08).

INPUT OFFSET

7–1

Red Channel Offset Adjust

A 7-bit offset binary word that sets the dc offset of the RED

channel. One LSB of offset adjustment equals approximately

one LSB change in the ADC offset. Therefore, the absolute

magnitude of the offset adjustment scales as the gain of the

channel is changed. A nominal setting of 31 results in the

channel nominally clamping the back porch (during the

clamping interval) to Code 00. An offset setting of 63 results

in the channel clamping to Code 31 of the ADC. An offset

setting of 0 clamps to Code –31 (off the bottom of the

range). Increasing the value of Red Offset DECREASES

the brightness of the channel.

7–1

Green Channel Offset Adjust

A 7-bit offset binary word that sets the dc offset of the

GREEN channel. See REDOFST (0B).

7–1

Blue Channel Offset Adjust

A 7-bit offset binary word that sets the dc offset of the

GREEN channel. See REDOFST (0B).

MODE CONTROL 1

Hsync Input Polarity Override

This register is used to override the internal circuitry

that determines the polarity of the Hsync signal going

into the PLL.

Table IX. Hsync Input Polarity Override Settings

Override Bit

Function

Hsync Polarity Determined by Chip

Hsync Polarity Determined by User

The default for Hsync polarity override is 0, (polarity

determined by chip.

HSPOL Hsync Input Polarity

A bit that must be set to indicate the polarity of the

Hsync signal that is applied to the PLL Hsync input.

Table X. Hsync Input Polarity Settings

HSPOL

Function

Active LOW

Active HIGH

Active LOW means the leading edge of the Hsync pulse is

negative-going. All timing is based on the leading edge of

Hsync, which is the FALLING edge. The rising edge has

no effect.

Active high is inverted from the traditional Hsync, with

a positive-going pulse. This means that timing will be

based on the leading edge of Hsync, which is now the

RISING edge.

The device will operate if this bit is set incorrectly, but the

internally generated clamp position, as established by

Clamp Placement (Register 05h), will not be placed as

expected, which may generate clamping errors.

The power-up default value is HSPOL = 1.

Hsync Output Polarity

One bit that determines the polarity of the Hsync output

and the SOG output. Table XI shows the effect of this

option. SYNC indicates the logic state of the sync pulse.

Table XI. Hsync Output Polarity Settings

Setting

SYNC

Logic 1 (Positive Polarity)

Logic 0 (Negative Polarity)

The default setting for this register is 0.

Active Hsync Override

This bit is used to override the automatic Hsync selection,

To override, set this bit to Logic 1. When overriding, the

active Hsync is set via Bit 3 in this register.

Table XII. Active Hsync Override Settings

Override

Result

Auto Determines the Active Interface

Override, Bit 3 Determines the Active Interface

The default for this register is 0.

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