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Active Hsync Select

This bit is used under two conditions. It is used to select

the active Hsync when the override bit is set, (Bit 4). Alter-

nately, it is used to determine the active Hsync when not

overriding but both Hsyncs are detected.

Table XIII. Active HSYNC Select Settings

Select

Result

HSYNC Input

Sync-on-Green Input

The default for this register is 0.

Vsync Output Invert

One bit that can invert the polarity of the Vsync output.

Table XIV shows the effect of this option.

Table XIV. Vsync Output Invert Settings

Setting

Vsync Output

No Invert

Invert

The default setting for this register is 1.

1 Active Vsync Override

This bit is used to override the automatic Vsync selection.

To override, set this bit to Logic 1. When overriding, the

active interface is set via Bit 0 in this register.

Table XV. Active Vsync Override Settings

Override

Result

Auto Determine the Active Vsync

Override, Bit 0 Determines the Active Vsync

The default for this register is 0.

0 Active Vsync Select

This bit is used to select the active Vsync when the over-

ride bit is set, (Bit 1).

Table XVI. Active Vsync Select Settings

Select

Result

Vsync Input

Sync Separator Output

The default for this register is 0.

7 Clamp Input Signal Source

A bit that determines the source of clamp timing.

Table XVII. Clamp Input Signal Source Settings

Clamp Function

Function

Internally Generated Clamp

Externally-Provided Clamp Signal

A 0 enables the clamp timing circuitry controlled by clamp

placement and clamp duration. The clamp position and

duration is counted from the leading edge of Hsync.

A 1 enables the external CLAMP input pin. The three

channels are clamped when the CLAMP signal is active.

The polarity of CLAMP is determined by the Clamp

Polarity bit (Register 0Fh, Bit 6).

The power-up default value is Clamp Function = 0.

6 Clamp Input Signal Polarity

A bit that determines the polarity of the externally pro-

vided CLAMP signal.

Table XVIII. Clamp Input Signal Polarity Settings

Clamp Function

Function

Active LOW

Active HIGH

A Logic 1 means that the circuit will clamp when CLAMP is

HIGH, and it will pass the signal to the ADC when CLAMP

is LOW.

A Logic 0 means that the circuit will clamp when CLAMP

is LOW, and it will pass the signal to the ADC when

CLAMP is HIGH.

The power-up default value is Clamp Polarity = 1.

5 Coast Select

This bit must be set to 0.

4 Coast Input Polarity Override

This register is used to override the internal circuitry that

determines the polarity of the coast signal going into

the PLL.

Table XIX. Coast Input Polarity Override Settings

Override Bit

Result

Coast Polarity Determined by Chip

Coast Polarity Determined by User

The default for coast polarity override is 0.

3 Coast Input Polarity

A bit to indicate the polarity of the COAST signal that is

applied to the PLL COAST input.

Table XX. Coast Input Polarity Settings

Coast Polarity

Function

Active LOW

Active HIGH

Active LOW means that the clock generator will ignore

Hsync inputs when COAST is LOW, and continue

operating at the same nominal frequency until COAST

goes HIGH.

Active HIGH means that the clock generator will ignore

Hsync inputs when COAST is HIGH, and continue

operating at the same nominal frequency until COAST

goes LOW.

This function needs to be used along with the COAST

polarity override bit, (Bit 4).

The power-up default value is 1.

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