INTEDG datasheet(98/478 Pages) MICROCHIP

98 / 478 page

PIC16(L)F1946/47

DS41414D-page 98

 2010-2012 Microchip Technology Inc.

PIR2: PERIPHERAL INTERRUPT REQUEST REGISTER 2

R/W-0/0

U-0

R/W-0/0

OSFIF

C2IF

C1IF

EEIF

BCLIF

LCDIF

—

CCP2IF

bit 7

bit 0

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

u = Bit is unchanged

x = Bit is unknown

-n/n = Value at POR and BOR/Value at all other Resets

‘1’ = Bit is set

‘0’ = Bit is cleared

bit 7

OSFIF: Oscillator Fail Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 6

C2IF: Comparator C2 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 5

C1IF: Comparator C1 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 4

EEIF: EEPROM Write Completion Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 3

BCLIF: MSSP1 Bus Collision Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 2

LCDIF: LCD Module Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

bit 1

Unimplemented: Read as ‘0’

bit 0

CCP2IF: CCP2 Interrupt Flag bit

1 = Interrupt is pending

0 = Interrupt is not pending

Note:

Interrupt flag bits are set when an interrupt

condition occurs, regardless of the state of

its corresponding enable bit or the Global

Enable bit, GIE, of the INTCON register.

User

software

should

ensure

the

appropriate interrupt flag bits are clear prior

to enabling an interrupt.

INTEDG Datasheet(PDF) 98 Page - Microchip Technology

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