ADE7953ACPZ datasheet(47/68 Pages) AD

47 / 68 page

Data Sheet

ADE7953

Rev. A | Page 47 of 68

INDICATION OF POWER DIRECTION

The ADE7953 includes sign indication on the active and reactive

energy measurements. Sign indication allows positive and nega-

tive energy to be identified and billed separately if required. It

also helps detect a miswiring condition. This feature is available

on both Current Channel A and Current Channel B. Power

direction information is available on both a dedicated output

pin (REVP) and via a set of internal registers and interrupts (see

the

section and the

section).

Reverse Power

Sign Indication

REVERSE POWER

The REVP pin (Pin 20) on the ADE7953 provides a reverse

power indicator. This pin can be configured to provide polarity

information about the active or reactive power on Current

Channel A or Current Channel B. The REVP output is high by

default and goes low if the angle between the voltage and current

input is greater than 90°. REVP is unlatched and, therefore,

returns high when the reverse power condition is no longer

true. Changes to the REVP output pin occur synchronously to

the falling edge of the CF1 pin by default (see

Figure 65

The measurement and channel indicated by the REVP pin are

selected by the configuration of the CF output. By default, the

REVP pin is configured to output synchronous to CF1 and

represents the measurement selected on CF1 using the CF1SEL

bits in the CFMODE register (Address 0x107). By default, this

measurement is the active power on Current Channel A. If the

CF1SEL bits are set to 0x0001, the REVP pin indicates the polarity

of the reactive power on Current Channel A. The REVP indicator

can be configured to output based on CF2 by setting the REVP_CF

bit in the CONFIG register (Address 0x102). In this configura-

tion, the CF2SEL bits in the CFMODE register determine the

measurement represented on the REVP output. If the selected

CF pin is configured to output another measurement, such as

apparent power or IRMS, the REVP output is disabled.

To improve the visibility of a reverse polarity condition if an

LED light is used, a 1 Hz pulse mode is available on the REVP

pin. In this mode, the REVP output pin is low by default and

outputs a 1 Hz pulse if the reverse polarity condition is true.

This pulse has a 50% duty cycle. Similar to normal mode, this

mode is also unlatched, and the REVP output returns high when

the reverse polarity is no longer true. To enable the REVP pulse

mode, the REVP_PULSE bit in the CONFIG register (Address

0x102) should be set to 1.

The REVP output pin is disabled in the corresponding no-load

condition. For example, if the reverse polarity information for

Current Channel A active power is present on the REVP pin and

the active energy on Current Channel A is in the no-load

condition, the REVP output is disabled and held in its current state.

SIGN INDICATION

The ADE7953 includes four sign indication bits that indicate the

polarity of the active power on Current Channel A (APSIGN_A),

the active power on Current Channel B (APSIGN_B), the

reactive power on Current Channel A (VARSIGN_A), and the

reactive power on Current Channel B (VARSIGN_B). These bits

are located in the ACCMODE register (Address 0x201 and

Address 0x301). All four bits are unlatched and read only. A low

reading (0) on any of these bits indicates that the correspond-ing

power reading is positive; a high reading (1) indicates that the

corresponding power reading is negative. These bits are enabled

by default and are disabled in the corresponding no-load

condition.

In addition to the sign indication bits, the ADE7953 also includes

four sign indication interrupts. If enabled, these interrupts cause

the IRQ pin to go low when the polarity of the power changes.

The interrupts are triggered on both positive-to-negative and

negative-to-positive polarity changes. These interrupts are dis-

abled by default and can be enabled by setting the APSIGN_A

and VARSIGN_A bits in the IRQENA register (Address 0x22C

and Address 0x32C), and the APSIGN_B and VARSIGN_B bits

in the IRQENB register (Address 0x22F and Address 0x32F).

See the

section.

ADE7953 Interrupts

Note that in absolute or positive-only accumulation mode, these

bits are fixed at 0. See the Active Energy Accumulation Modes

section and the Reactive Energy Accumulation Modes section.

CF1

ENTER

REVERSE

CONDITION

REVP

CURRENT AND

VOLTAGE

INPUTS

EXIT

REVERSE

CONDITION

REVP

HIGH

REVP

LOW

Figure 65. REVP Output

ADE7953ACPZ Datasheet(PDF) 47 Page - Analog Devices

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