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SPT5400SCP Datasheet(PDF) 3 Page - Fairchild Semiconductor |
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SPT5400SCP Datasheet(HTML) 3 Page - Fairchild Semiconductor |
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3 / 8 page ![]() 3 5/15/00 SPT5400 TEST LEVEL CODES All electrical characteristics are subject to the following conditions: All parameters having min/max specifi- cations are guaranteed. The Test Level column indicates the specific device testing actually performed during pro- duction and Quality Assurance inspec- tion. Any blank section in the data column indicates that the specification is not tested at the specified condition. TEST LEVEL TEST PROCEDURE I 100% production tested at the specified temperature. II 100% production tested at TA = +25 °C, and sample tested at the specified temperatures. III QA sample tested only at the specified temperatures. IV Parameter is guaranteed (but not tested) by design and characteriza- tion data. V Parameter is a typical value for information purposes only. VI 100% production tested at TA = +25 °C. Parameter is guaranteed over specified temperature range. Figure 1 – Timing Diagram t5 t1 t6 t2 t9 t10 t7 t8 t4 t3 A0–A2 D0–D12 LD CS WR NOTES: 1. All input rise and fall times are measured from 10% to 90% of +5 V. tR = tF = 5 ns. 2. If LD is activated while WR is low, LD must stay low for t3 or longer after WR goes high. Table I – Timing Parameters PARAMETER SYMBOL MIN TYP MAX UNIT CS Pulse Width Low t1 50 ns WR Pulse Width Low t2 50 ns LD Pulse Width Low t3 50 ns CLR Pulse Width Low t4 100 ns CS to WR Low t5 0ns CS High to WR High t6 0ns Data Valid to WR Setup t7 20 ns Data Valid to WR Hold t8 0ns Address Valid to WR Setup t9 10 ns Address Valid to WR Hold t10 0ns |
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