8

5/15/00

SPT5400

ORDERING INFORMATION

PART NUMBER

TEMPERATURE RANGE

PACKAGE

SPT5400SCP

0 to +70

°C

44L PLCC

PIN ASSIGNMENTS

Top View

44

1

REFAB

AGNDAB

LDAB

LDCD

CS

WR

A2

A1

REFGH

AGNDGH

GND

LDGH

LDEF

D0

D1

D2

6

7

17

18

28

29

39

40

PIN FUNCTIONS

Name

Function

CLR

Clear input (active low). Driving this asynchronous

input low sets the content of all latches to 1000hex.

All DAC outputs are reset to AGNDxx.

AGNDCD

Analog ground for DAC C and DAC D.

REFCD

Reference voltage input for DAC C and DAC C.

Bypass to AGNDCD with a 0.1 to 1

µF capacitor.

Negative power supply, –5 V (two pins). Connect

both pins to the supply voltage. Bypass each pin to

the system analog ground with a 0.1

µF capacitor.

DAC D output voltage.

DAC C output voltage.

DAC B output voltage.

DAC A output voltage.

Positive power supply, +5 V (two pins). Connect

both pins to the supply voltage. Bypass each pin to

the system analog ground with a 0.1

µF capacitor.

REFAB

Reference voltage input for DAC A and DAC B.

Bypass to AGNDAB with a 0.1 to 1

µF capacitor.

AGNDAB

Analog ground for DAC A and DAC B.

LDAB

Load input (active low). Driving this asynchronous

input low transfers the contents of the input latches

A and B to the respective DAC latches.

LDCD

Load input (active low). Driving this asynchronous

input low transfers the contents of the input latches

C and D to the respective DAC latches.

CS

Chip select (active low).

WR

into the DAC input latch selected by A0–A2.

A2

Address bit 2.

A1

Address bit 1.

A0

Address bit 0.

D12–D0

Data bits 12–0. (D0 = LSB)

LDEF

Load input (active low). Driving this asynchronous

input low transfers the contents of the input latches

E and F to the respective DAC latches.

LDGH

Load input (active low). Driving this asynchronous

input low transfers the contents of the input latches

G and H to the respective DAC latches.

GND

Digital ground.

AGNDGH

Analog ground for DAC G and DAC H.

REFGH

Reference voltage input for DAC G and DAC H.

Bypass to AGNDGH with a 0.1 to 1

µF capacitor.

DAC H output voltage.

DAC G output voltage.

DAC F output voltage.

DAC E output voltage.

REFEF

Reference voltage input for DAC E and DAC F.

Bypass to AGNDEF with a 0.1 to 1

µF capacitor.

AGNDEF

Analog ground for DAC E and DAC F.

Name

Function

LIFE SUPPORT POLICY

FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS

WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein:

1. Life support devices or systems are devices or systems which, (a) are

intended for surgical implant into the body, or (b) support or sustain life,

and whose failure to perform, when properly used in accordance with

instructions for use provided in the labeling, can be reasonably

expected to result in a significant injury to the user.

2. A critical component is any component of a life support device or

system whose failure to perform can be reasonably expected to cause

the failure of the life support device or system, or to affect its safety or

effectiveness.

DISCLAIMER

FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO

IMPROVE RELIABILITY, FUNCTION OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR

USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR

THE RIGHTS OF OTHERS.

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© Copyright 2002 Fairchild Semiconductor Corporation