AX2000 datasheet(87/262 Pages) MICROSEMI

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Axcelerator Family FPGAs

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PLLRCLK and PLLHCLK

PLLRCLK (PLLHCLK) is used to drive global resource CLK (HCLK) from a PLL (Figure 2-44).

Using Global Resources with PLLs

Each global resource has an associated PLL at its root. For example, PLLA can drive HCLKA, PLLE can

drive CLKE, etc. (Figure 2-45).

In addition, each clock pin of the package can be used to drive either its associated global resource or

PLL. For example, package pins CLKEP and CLKEN can drive either the RefCLK input of PLLE or

CLKE.

There are two macros required when interfacing the embedded PLLs with the global resources: PLLINT

and PLLOUT.

PLLINT

This macro is used to drive the RefCLK input of the PLL internally from user signals.

PLLOUT

This macro is used to connect either the CLK1 or CLK2 output of a PLL to the regular routing network

(Figure 2-46).

Figure 2-44 • PLLRCLK and PLLHCLK

Figure 2-45 • Example of HCLKA Driven from a PLL with External Clock Source

Figure 2-46 • Example of PLLINT and PLLOUT Usage

PLLRCLK

PLLHCLK

Clock

Network

CLK1

CLK2

RefCLK

PLL

HCLKAP

HCLKAN

PLLHCLK

HCLKA

Network

CLK1

CLK2

RefCLK

PLLA

PLLINT

PLLHCLK

PLLOUT

HCLKA

Network

CLK1

CLK2

RefCLK

PLLA

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