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NB669 Datasheet(PDF) 11 Page - Monolithic Power Systems |
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NB669 Datasheet(HTML) 11 Page - Monolithic Power Systems |
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11 / 19 page ![]() NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO NB669 Rev. 1.01 www.MonolithicPower.com 11 7/23/2013 MPS Proprietary Information. Patent Protected. Unauthorized Photocopy and Duplication Prohibited. © 2013 MPS. All Rights Reserved. Figure 3—Light Load Operation As the output current increases from the light load condition, the time period within which the current modulator regulates becomes shorter. The HS-FET is turned ON more frequently. Hence, the switching frequency increases correspondingly. The output current reaches the critical level when the current modulator time is zero. The critical level of the output current is determined as follows: IN OUT OUT OUT SW IN (V V ) V I 2L F V −× = ×× × (1) It turns into PWM mode once the output current exceeds the critical level. After that, the switching frequency stays fairly constant over the output current range. Jitter and FB Ramp Slope Jitter occurs in both PWM and skip modes when noise in the VFB ripple propagates a delay to the HS-FET driver, as shown in Figures 4 and 5. Jitter can affect system stability, with noise immunity proportional to the steepness of VFB’s downward slope. However, VFB ripple does not directly affect noise immunity. V RE F V FB HS D river VNOISE J itter V S L O PE1 Figure 4—Jitter in PWM Mode V FB HS D river Jitter V REF V SL O P E 2 VNOISE Figure 5—Jitter in Skip Mode Selecting the Output Capacitors The traditional constant-on-time control scheme is intrinsically unstable if output capacitor’s ESR is not large enough as an effective current-sense resistor. Ceramic capacitors usually can not be used as output capacitor. Figure 6 shows an equivalent circuit in PWM mode with the HS-FET off. To realize the stability, the ESR value should be chosen as follow: SW ON ESR OUT TT 0.7 2 R C + ×π ≥ (2) TSW is the switching period. R R ESR CAP FB VOUT L VOUT SW Figure 6—Simplified Circuit in PWM Mode The NB669 has built in internal ramp compensation to make sure the system is stable even without the help of output capacitor’s ESR; and thus the pure ceramic capacitor solution can be applicant. The pure ceramic capacitor solution can significantly reduce the output ripple, total BOM cost and the board area. Configuring the EN Control The NB669 has two enable pins to control the on/off of the internal regulators. ENLDO is used to enable or disable the whole |
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