NB669, 24V, HIGH CURRENT SYNCHRONOUS BUCK CONVERTER WITH LDO

NB669 Rev. 1.01

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16

7/23/2013

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current, and that the peak inductor current is

below the maximum switch current limit. The

inductance value can be calculated by:

OUT

OUT

SW

L

IN

VV

L(1

)

FI

V

=× −

×Δ

(15)

current.

The inductor should not saturate under the

maximum inductor peak current, where the peak

inductor current can be calculated by:

OUT

OUT

LP

OUT

SW

IN

VV

II

(1

)

2F

L

V

=+

× −

×

(16)

PCB Layout Guide

The following guidelines should be followed when

designing the PC board for the NB669:

1. The high current paths (GND, IN, and SW)

should be placed very close to the device

with short, direct and wide traces.

2. Put the input capacitors as close to the IN

and GND pins as possible.

3. Put the decoupling capacitor as close to the

VCC and AGND pins as possible. Place the

Cap close to AGND if the distance is long.

And place >3 Vias if via is required to reduce

the leakage inductance.

4. Keep the VOUT sensing trace far away from

the SW node.Vias should also be avoided on

the VOUT sensing trace.

5. Keep the BST voltage path (BST, C3, and

SW) as short as possible.

6. Keep the IN and GND pads connected with

large copper and use at least two layers for

IN and GND trace to achieve better thermal

performance. Also, add several Vias with

10mil_drill/18mil_copper_width close to the

IN and GND pads to help on thermal

dissipation.

7. AGND

connects

PGND

with

KELVIN

Connecting.

8. Four-layer layout is strongly recommended to

achieve better thermal performance.

Note:

Please refer to the PCB Layout Application Note

for more details.