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AM79C30AVC Datasheet(PDF) 86 Page - Advanced Micro Devices |
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AM79C30AVC Datasheet(HTML) 86 Page - Advanced Micro Devices |
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86 / 101 page  86 Am79C30A/32A Data Sheet IOM-2 Master Mode Timing IOM-2 Slave Mode Timing Notes: *The +163-ns value can occur once per frame for digital phase lock loop correction. **CL = 150 pF Parameter Signal Abbr Test Condition Min Max Units Data Clock Rise/Fall SCLK tR,tF CL = 150 pF 50 ns Clock Period SCLK tSCL 1.536 MHz 487 815 ns ± 100 PPM ±163 ns* Pulse Width SCLK tWH, tWL 260 ns Frame Sync SFS tR,tF CL = 150 pF 50 ns Frame Sync Setup/Clock SFS tSF CL = 150 pF 50 ns Frame Sync Delay/Clock SFS tFD CL = 150 pF 0 ns Frame Sync Hold/Clock SFS tFH CL = 150 pF 50 tWL + 50 ns Frame Delay SFS tDF CL = 150 pF –tWL 50 ns Data Delay/Clock SBOUT tDSC CL = 150 pF 100 ns Data Hold/Clock SBOUT tDHC CL = 150 pF 70 ns Data Setup SBIN tSD tWH + 20 ns Data Hold SBIN tHD 50 ns Parameter Signal Abbr Min Max Units Data Clock Rise/Fall SCLK tR,tF 60 ns Clock Frequency (1/period) SCLK 1/tSCLK 1.536 MHz ±100 PPM ±163 ns* Hz Clock Delay High/Low BCL tBLH, tBHL 30 ns Pulse Width SCLK tWH, tWL 240 ns Frame Sync Rise/Fall SFS tR,tF 60 ns Frame Set-up SFS tSF 70 ns Frame Hold/Clock SFS tFH 20 ns Frame Delay/Clock SFS tFD 0ns Frame Width High SFS tWFH 130 ns Frame Width Low SFS tWFL tSCLK ns Data Delay/Clock SBOUT tDSC 100** ns Data Hold/Clock SBOUT tDHC 70 ns Data Set-up SBIN tSD tWH + 20 ns Data Hold SBIN tHD 50 ns |
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