AM79C30AVC datasheet(12/101 Pages) AMD

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Am79C30A/32A Data Sheet

Table 4.

Format of the Interrupt Register (IR), Read Only

Bit

Interrupt Generated/Action Required

Interrupt Mask

D-channel transmit threshold interrupt/load D-channel Transmit buffer

DMR1 bit 0

D-channel receive threshold interrupt/read D-channel Receive buffer

DMR1 bit 1

D-channel status interrupt/read DSR1

Source

Cause

DSR1 bit 0

Valid Address (VA) or End of Address (EOA)

DMR3 bit 0

DSR1 bit 1

When a closing flag is received or a receive error occurs

DMR1 bit 3

DSR1 bit 6

When a closing flag is transmitted DMR3 bit 1

DMR3 bit 1

D-channel error interrupt/read DER and DSR2 bit 2

Source

Cause

DER bit 0

Current received packet has been aborted

DMR2 bit 0

DER bit 1

Non-integer number of bytes received

DMR2 bit 1

DER bit 2

Collision abort detected

DMR2 bit 2

DER bit 3

FCS error

DMR2 bit 3

DER bit 4

Overflow error

DMR2 bit 4

DER bit 5

Underflow error

DMR2 bit 5

DER bit 6

Overrun error

DMR2 bit 6

DER bit 7

Underrun error

DMR2 bit 7

DSR2 bit 2

Receive packet lost

DMR3 bit 6

Bb or Bc byte available or buffer empty interrupt/read or write Bb or Bc buffers

MCR4 bit 3

LIU status interrupt/read LSR

Source

Cause

LSR bit 3

Change of state to F3

LMR2 bit 3

LSR bit 4

Change of state from/to F7

LMR2 bit 6

LSR bit 5

Change of state from/to F8

LMR2 bit 4

LSR bit 7

HSW change of state

LMR2 bit 5

D-channel status interrupt/read DSR2

Source

Cause

DSR2 bit 0

Last byte of received packet

DMR3 bit 2

DSR2 bit 1

Receive byte available

DMR3 bit 3

DSR2 bit 3

Last byte transmitted

DMR3 bit 4

DSR2 bit 4

Transmit buffer available

DMR3 bit 5

DSR2 bit 7

Start of second packet

EFCR bit 1

Multiframe or PP interrupt/read MFSB and PPSR

Source

Cause

MFSB bit 5

S-data available

MF bit 1

MFSB bit 6

Q-bit buffer empty

MF bit 2

MFSB bit 7

Multiframe change of state (in/out of sync)

MF bit 3

PPSR bit 0

Monitor receive, data available

PPIER bit 0

PPSR bit 1

Monitor transmit, buffer available

PPIER bit 1

PPSR bit 2

Monitor EOM received

PPIER bit 2

PPSR bit 3

Monitor abort received

PPIER bit 3

PPSR bit 4

C/I channel 0, data change

PPIER bit 4

PPSR bit 5

C/I channel 1, data change

PPIER bit 5

PPSR bit 6

IOM-2 timing request

PPIER bit 6

AM79C30AVC Datasheet(PDF) 12 Page - Advanced Micro Devices

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