AM79C984 datasheet(13/44 Pages) AMD

13 / 44 page

P R E L I M I N A R Y

Am79C984A

an I/O and must be pulled to VDD via a minimum equiv-

alent resistance of 1 k

Ω. When the eIMR device expan-

sion port is conﬁgured for IMR+ mode, COL is an input

driven by an external arbiter.

Control Port

AMODE

AUI Mode

Input

At reset, this pin sets the AUI port to either normal or

reversed mode. If AMODE is LOW at the rising edge of

RST, the AUI port is set to the normal mode; if AMODE

is HIGH, the AUI port is set to the reversed mode.

SCLK

Serial Clock In

Input

Serial data (input or output) is clocked (in or out) on the

rising edge of the signal on this pin. SCLK is asynchro-

nous to CLK and can operate at frequencies up to 10

MHz.

Serial In

Input

The SI pin is used as a test/control serial input port.

Control commands are clocked in on this pin synchro-

nous to SCLK input.

At reset, SI sets the state of the Automatic Polarity Re-

versal function. If SI is HIGH at the rising edge of RST,

Automatic Polarity Reversal is disabled. If SI is LOW at

the rising edge of RST, Automatic Polarity Reversal is

enabled.

Serial Out

Output

The SO pin is used as a control command serial output

port. Responses to control commands are clocked out

on this pin synchronous to the SCLK input.

LED Interface

LDA0-4, LDB0-4

LED Drivers

Output, Open Drain

LDA0-4 and LDB0-4 drive LED Bank A and LED Bank B,

respectively. LDA0 and LDB0 indicate the status of the

AUI port; LDA1-4 and LDB1-4 indicate the status of the

four TP ports. The port attributes monitored by LDA0-4

and LDB0-4 are programmed by three pins, LDC0-2.

LDGA

Global LED Driver, Bank A

Output, Open Drain

LDGA is the Global LED driver for LED Bank A. The

signal represents global CRS or COL conditions. In a

multiple-eIMR conﬁguration, LDGA from each of the

eIMR devices can be tied together to drive a single glo-

bal LED in Bank A.

LDGB

Global LED Driver, Bank B

Output, Open Drain

LDGB is the Global LED driver for LED Bank B. The

signal represents global CRS or JAB conditions. In a

multiple eIMR conﬁguration, LDGB from each of the

eIMR devices can be tied together to drive a single glo-

bal LED in Bank B.

LDC0-2

LED Control

Input

These pins select the attributes that will be displayed

on LDA0-4, LDB0-4, LDGA, and LDGB. If an LED is pro-

grammed to display two attributes, the attribute associ-

ated with the periodic blink takes precedence.

ACT0-7

Activity Display

Output

These signals drive the activity LEDs, which indicate

the percentage of network utilization. The display is up-

dated every 250 ms.

Miscellaneous Pins

RST

Reset

Input, Active LOW

When RST is LOW, the eIMR device resets to its default

state. On the rising (trailing) edge of RST, the eIMR also

monitors the state of the SELI0-1, SI, and AMODE pins,

to conﬁgure the operating mode of the device. In multi-

ple eIMR systems, the falling (leading) edge of the RST

signal must be synchronized to CLK.

CLK

Master Clock In

Input

This pin is a 20-MHz clock input.

REXT

External Reference

Input

This pin is used for an internal current reference. It must

be tied to VDD via a 13-k

Ω resistor with 1% tolerance.

VDD

Power

Power Pin

This pin supplies power to the device.

AM79C984 Datasheet(PDF) 13 Page - Advanced Micro Devices

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