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AS8650B Datasheet(PDF) 33 Page - ams AG

No. de pieza AS8650B
Descripción Electrónicos  High-efficient Power Management Device with High-speed CAN Interface
PDF  47 Pages
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Fabricante Electrónico  AMSCO [ams AG]
Página de inicio  http://www.ams.com
Logo AMSCO - ams AG

AS8650B Datasheet(HTML) 33 Page - ams AG

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Revision 1.1
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AS8650B
Datasheet - Application In form atio n
8.1.1 SPI Write Operation
The SPI write operation begins with clock polarity selection at negative edge of CS, given in Table 20. Once the clock polarity is selected the SPI
write command is given by providing ‘0’ in R/W bit of the header field in first sampling edge at SDI pin. The 5 bits address of register to be written
is provided at SDI pin in next five consecutive sampling edges of SCLK. The first 2 bits in header fields are reserved and set to ‘0’. The data to be
written is followed by last bit of header field. With each sampling edge a bit is sampled starting from MSB to LSB. During complete SPI write
operation the CS has to be ‘low’. The SPI write operation ends with positive edge of CS. The wave form for SPI write operation with single data
byte is shown in Figure 16 and Figure 17.
Figure 16. SPI Write Operation with Negative Clock Polarity and 1 Byte of Data Field
Figure 17. SPI Write Operation with Positive Clock Polarity and 1 Byte of Data Field
R1
R0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
SCLK
SDI
SDO
CS
Sampling Edge
High Impedance Sate
SCLK
SDI
SDO
CS
R1
R0
A4
A3
A2
A1
A0
D7
D6
D5
D4
D3
D2
D1
D0
Sampling Edge
High Impedance Sate



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