ICS1889 datasheet(4/35 Pages) ICST

4 / 35 page

ICS1889

Transmit Clock Synthesizer

The ICS1889 synthesizes the transmit clock using a PLL to

produce 25 MHz and 125 MHz clocks. This allows the use of

a low cost 25 MHz crystal or a low jitter reference frequency

source.

Receive Clock Recovery

The receive clock recovery logic monitors the receive line and

detects a receive signal. The logic, which includes a PLL,

extracts data and clock from the 100Base-FX, 125 Mbps,

NRZI bit stream. In the event that the PLL is unable to lock on

to the receive signal, it generates a not locked signal. The

transmit clock synthesizer provides a center frequency

reference for operation of the clock recovery circuit in the

absence of data. The receive signal detected and not

locked signals are both used by the logic which monitors the

receive channel for errors.

Carrier Detector & Framer

The carrier detector examines the receive serial bit stream

looking for the SSD, the JK symbol pair. In the idle state,

IDLE symbols (all logic ones) will be received. If the carrier

detector detects a logic zero in the bit stream, it examines the

following bits looking for the first two non-contiguous zeroes,

confirms that the first 5-bits form the J symbol (11000) and

asserts carrier detect. At this point the serial data is framed

and the second symbol is checked to confirm the K symbol

(10001). If successful, the following framed data (symbols)

are presented to the 4B5B decoder. If the JK pair is not

confirmed, the false carrier detect bit is asserted in the

QuickPoll Register and the idle state is reentered.

ICS1889 Datasheet(PDF) 4 Page - Integrated Circuit Systems