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R5F6451MLFD Datasheet(PDF) 90 Page - Renesas Technology Corp |
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R5F6451MLFD Datasheet(HTML) 90 Page - Renesas Technology Corp |
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90 / 122 page ![]() R01DS0072EJ0120 Rev.1.20 Page 90 of 116 Aug 07, 2013 R32C/151 Group 5. Electrical Characteristics Timing Requirements (VCC = 3.0 to 5.5 V, VSS = 0 V, and Ta = Topr, unless otherwise noted) Figure 5.5 Flash Memory CPU Rewrite Mode Timing Table 5.15 Flash Memory CPU Rewrite Mode Timing Symbol Characteristics Value Unit Min. Max. tcR Read cycle time 200 ns tsu(S-R) Chip-select setup time before read 200 ns th(R-S) Chip-select hold time after read 0ns tsu(A-R) Address setup time before read 200 ns th(R-A) Address hold time after read 0ns tw(R) Read pulse width 100 ns tcW Write cycle time 200 ns tsu(S-W) Chip-select setup time before write 0ns th(W-S) Chip-select hold time after write 30 ns tsu(A-W) Address setup time before write 0ns th(W-A) Address hold time after write 30 ns tw(W) Write pulse width 50 ns Chip select Address RD t h(R-S) Read cycle t w(R) t su(S-R) t h(R-A) t su(A-R) Write cycle Chip select Address WR t h(W-S) t w(W) t su(S-W) t h(W-A) t su(A-W) t cW t cR |
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