RM0352 datasheet(117/138 Pages) STMICROELECTRONICS

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RM0352

UART (universal asynchronous receive transmit)

137

The transmit and receive data flow interrupts UARTRXINTR and UARTTXINTR have been

separated from the status interrupts. This enables use of the UARTRXINTR and

UARTTXINTR so that data can be read or written in response to the FIFO trigger levels.

The error interrupt, UARTEINTR, can be triggered when there is an error in the reception of

data. A number of error conditions are possible.

The modem status interrupt, UARTMSINTR, is a combined interrupt of all the individual

modem status signals.

The status of the individual interrupt sources can be read either from the raw interrupt status

Section 12.6.11 on page 131 or from the masked interrupt status

Section 12.6.12 on page 132.

12.4.1

UARTMSINTR

The modem status interrupt is asserted if any of the modem status signals (nUARTCTS,

nUARTDCD, nUARTDSR, and nUARTRI) change. It is cleared by writing a 1 to the

corresponding bit(s) in the interrupt clear register, UARTICR - see

Section 12.6.13 on page

133, depending on the modem status signals that generated the interrupt.

12.4.2

UARTRXINTR

The receive interrupt changes state when one of the following events occurs:

•

If the FIFOs are enabled and the receive FIFO reaches the programmed trigger level.

When this happens, the receive interrupt is asserted HIGH. The receive interrupt is

cleared by reading data from the receive FIFO until it becomes less than the trigger

level, or by clearing the interrupt.

•

If the FIFOs are disabled (have a depth of one location) and data is received thereby

filling the location, the receive interrupt is asserted HIGH. The receive interrupt is

cleared by performing a single read of the receive FIFO, or by clearing the interrupt.

12.4.3

UARTTXINTR

The transmit interrupt changes state when one of the following events occurs:

•

If the FIFOs are enabled and the transmit FIFO is equal to or lower than the

programmed trigger level then the transmit interrupt is asserted HIGH. The transmit

interrupt is cleared by writing data to the transmit FIFO until it becomes greater than the

trigger level, or by clearing the interrupt.

•

If the FIFOs are disabled (have a depth of one location) and there is no data present in

the transmitters single location, the transmit interrupt is asserted HIGH. It is cleared by

performing a single write to the transmit FIFO, or by clearing the interrupt.

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