RM0312 datasheet(118/275 Pages) STMICROELECTRONICS

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16-bit general purpose timer (TIM2/TIM3)

RM0312

118/275

DocID022352 Rev 3

The counter counts once each 2 ETR rising edges.

The delay between the rising edge on ETR and the actual reset of the counter is due to the

resynchronization circuit on the ETRP signal.

Figure 35. Control circuit in external clock mode 2

17.4.5

Trigger synchronization

There are four trigger inputs (refer to Table 33: Glossary of internal timer signals on

page 103):

•

ETR

•

TI1

•

TI2

•

TRGO from other timers

The TIMx timer can be synchronized with an external trigger in three modes: trigger

standard mode, trigger reset mode and trigger gated mode.

Trigger standard mode

The counter can start in response to an event on a selected input.

In the following example, the up-counter starts in response to a rising edge on TI2 input:

•

Configure the channel 2 to detect rising edges on TI2. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC2F=0b0000). The capture

prescaler is not used for triggering, so you don’t need to configure it. TI2S bits are

selecting the input capture source only, and don’t need to be configured too. Write

CC2P=0 in TIMx_CCER1 register to select rising edge polarity.

•

Configure the timer in trigger mode by writing SMS=0b110 in the TIMx_SMCR register.

Select TI2 as the input source by writing TS=0b110 in the TIMx_SMCR register.

When a rising edge occurs on TI2, the counter starts counting on the internal clock and the

TIF flag is set.

The delay between the rising edge on TI2 and the actual reset of the counter is due to the

resynchronization circuit on TI2 input.

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER

ETR

CNT_EN

fMASTER

ETRP

ETRF

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