RM0312 datasheet(120/275 Pages) STMICROELECTRONICS

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16-bit general purpose timer (TIM2/TIM3)

RM0312

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DocID022352 Rev 3

Trigger gated mode

The counter can be enabled depending on the level of a selected input.

In the following example, the up-counter counts only when TI1 input is low:

Configure the channel 1 to detect low levels on TI1. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC1F=0b0000). The capture

prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits

select the input capture source only, and do not need to be configured either. Write

CC1P=1 in TIMx_CCER1 register to validate the polarity (and detect low level only).

Configure the timer in trigger gated mode by writing SMS=0b101 in TIMx_SMCR

Enable the counter by writing CEN=1 in the TIMx_CR1 register (in trigger gated mode,

the counter doesn’t start if CEN=0, whatever is the trigger input level).

The counter starts counting on the internal clock as long as TI1 is low and stops as soon as

TI1 becomes high. The TIF flag is set both when the counter starts or stops.

The delay between the rising edge on TI1 and the actual reset of the counter is due to the

resynchronization circuit on TI1 input.

Figure 38. Control circuit in trigger gated mode

Combining trigger modes with external clock mode 2

The external clock mode 2 can be used in addition to another trigger mode. In this case,

ETR is used as external clock input, and another input can be selected as trigger input (in

trigger standard mode, trigger reset mode or trigger gated mode). Take care that you must

not select ETR as TRGI (through the TS bits in TIMx_SMCR register).

In the following example, the up-counter counts at each rising edge on ETR as soon as a

rising edge has occured on TI1 (standard trigger mode with external ETR clock):

•

Configure the external trigger input circuit by writing the TIMx_ETR register. In this

example, we don’t need any filter and write ETF=0b0000. Write ETPS=00 to disable

the prescaler, ETP=0 to detect rising edges on ETR and ECE=1 to enable the external

clock mode 2.

•

Configure the channel 1 to detect rising edges on TI1. Configure the input filter duration

(in this example, we don’t need any filter, so we keep IC1F=0b0000). The capture

prescaler is not used for triggering, so you don’t need to configure it. The CC1S bits

select the input capture source only, and do not need to be configured either. Write

CC1P=0 in TIMx_CCER1 register to select rising edge polarity.

COUNTER CLOCK = CK_CNT = CK_PSC

COUNTER REGISTER

35 36 37 38

32 33

TI1

CNT_EN

TIF

Write TIF=0

RM0312 Datasheet(PDF) 120 Page - STMicroelectronics

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