RM0312 datasheet(139/275 Pages) STMICROELECTRONICS

139 / 275 page

DocID022352 Rev 3

139/275

RM0312

16-bit general purpose timer (TIM2/TIM3)

170

When a break occurs (selected level on the break input):

•

The MOE bit is cleared asynchronously, putting the outputs in inactive state, idle state

or in reset state (selected by the OSSI bit). This feature functions even if the MCU

oscillator is off.

•

Each output channel is driven with the level programmed in the OISi bit in the

TIMx_OISR register as soon as MOE=0. If OSSI=0 then the timer releases the enable

output else the enable output remains high.

•

The break status flag (BIF bit in the TIMx_SR1 register) is set. An interrupt can be

generated if the BIE bit in the TIMx_IER register is set.

•

If the AOE bit in the TIMx_BKR register is set, the MOE bit is automatically set again at

the next update event UEV. This can be used to perform a regulation, for instance.

Else, MOE remains low until you write it to ‘1’ again. In this case, it can be used for

security and you can connect the break input to an alarm from power drivers, thermal

sensors or any security components.

Note:

The break inputs are acting on level. Thus, the MOE cannot be set while the break input is

active (neither automatically nor by software). In the meantime, the status flag BIF cannot

be cleared.

The break can be generated by the break input (BKIN) which has a programmable polarity

and can be enabled or disabled by setting or resetting the BKE bit in TIMx_BKR register.

In addition to the break inputs and the output management, a write protection has been

implemented inside the break circuit to safeguard the application. It allows you to freeze the

configuration of several parameters (OCi polarities and state when disabled, OCiM

configurations, break enable and polarity). You can choose from 3 levels of protection

selected by the LOCK bits in the TIMx_BKR register. The LOCK bits can be written only

once after an MCU reset.

Figure 60 shows an example of behavior of the outputs in response to a break.

Figure 60. Behavior of outputs in response to a break

17.5.9

Clearing the OCiREF signal on an external event

The OCiREF signal of a given channel can be cleared when a high level is detected on

ETRF (if OCiCE=‘1’ in the TIMx_CCMRi register, one enable bit per channel). The OCiREF

signal remains low until the next UEV update event occurs. This function can be used in

output compare mode and PWM mode only, it does not work in forced mode.

It can be connected to the output of a comparator and be used for current handling, for

instance.

OCiREF

BREAK (MOE

OCi

(CCiP=0, OISi=1)

OCi

(CCiP=0, OISi=0)

OCi

(CCiP=1, OISi=1)

OCi

(CCiP=1, OISi=0)

)

RM0312 Datasheet(PDF) 139 Page - STMicroelectronics

RM0312 Datasheet(HTML) 139 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL