RM0312 datasheet(149/275 Pages) STMICROELECTRONICS

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RM0312

16-bit general purpose timer (TIM2/TIM3)

170

17.7.7

Status register 2 (TIMx_SR2)

Address offset: 0x06

Reset value: 0x00

Bit 1 CC1IF: Capture/Compare 1 interrupt flag

– If channel CC1 is configured as output:

This flag is set by hardware when the counter matches the compare value. It is cleared by software.

0: No match.

1: The content of the counter TIMx_CNT has matched the content of the TIMx_CCR1 register.

– If channel CC1 is configured as input:

This bit is set by hardware on a capture. It is cleared by software or by reading the TIMx_CCR1L

0: No input capture occurred.

1: The counter value has been captured in TIMx_CCR1 register (An edge has been detected on IC1

which matches the selected polarity).

Bit 0 UIF: Update interrupt flag

This bit is set by hardware on an update event. It is cleared by software.

0: No update occurred.

1: Update interrupt pending. This bit is set by hardware when the registers are updated:

– At overflow if UDIS=0 in the TIMx_CR1 register.

– When CNT is re-initialized by software using the UG bit in TIMx_EGR register, if URS=0 and

UDIS=0 in the TIMx_CR1 register.

654

3210

Reserved

CC2OF

CC1OF

Reserved

rc_w0

Bits 7:3 Reserved

Bit 2 CC2OF: Capture/Compare 2 overcapture flag

Refer to CC1OF description

Bit 1 CC1OF: Capture/Compare 1 overcapture flag

This flag is set by hardware only when the corresponding channel is configured in input capture

mode. It is cleared by software by writing it to ‘0’.

0: No overcapture has been detected.

1: The counter value has been captured in TIMx_CCR1 register while CC1IF flag was already set

Bit 0 Reserved

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