RM0312 datasheet(150/275 Pages) STMICROELECTRONICS

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16-bit general purpose timer (TIM2/TIM3)

RM0312

150/275

DocID022352 Rev 3

17.7.8

Event generation register (TIMx_EGR)

Address offset: 0x07

Reset value: 0x00

654

3210

Reserved

CC2G

CC1G

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Bit 7 BG: Break generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action.

1: A break event is generated. MOE bit is cleared and BIF flag is set. An interrupt is generated if

enabled by the BIE bit.

Bit 6 TG: Trigger generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action.

1: The TIF flag is set in TIMx_SR1 register. An interrupt is generated if enabled by the TIE bit.

Bits 5:3 Reserved

Bit 2 CC2G: Capture/Compare 2 generation

Refer to CC1G description

Bit 1 CC1G: Capture/Compare 1 generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: A capture/compare event is generated on channel 1:

– If the CC1 channel is configured in output mode:

CC1IF flag is set, and the corresponding interrupt request is sent if enabled.

– If the CC1 channel configured in input mode:

The current value of the counter is captured in the TIMx_CCR1 register. The CC1IF flag is set, and

the corresponding interrupt request is sent if enabled. The CC1OF flag is set if the CC1IF flag was

already high.

Bit 0 UG: Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1: Re-initializes the counter and generates an update of the registers. Note that the prescaler

counter is cleared too.

RM0312 Datasheet(PDF) 150 Page - STMicroelectronics