RM0312 datasheet(169/275 Pages) STMICROELECTRONICS

169 / 275 page

DocID022352 Rev 3

169/275

RM0312

8-bit basic timer (TIM4)

170

18.5.6

Event generation register (TIM4_EGR)

Address offset: 0x05

Reset value: 0x00

18.5.7

Counter (TIM4_CNTR)

Address offset: 0x06

Reset value: 0x00

18.5.8

Prescaler register (TIM4_PSCR)

Address offset: 0x07

Reset value: 0x00

654

3210

Reserved

Bit 7 Reserved

Bit 6 TG: Trigger generation

This bit is set by software in order to generate an event, it is automatically cleared by hardware.

0: No action

1: The TIF flag is set in TIM4_SR1 register. An interrupt is generated if enabled by the TIE bit.

Bits 5:1 Reserved

Bit 0 UG: Update generation

This bit can be set by software, it is automatically cleared by hardware.

0: No action

1: Re-initializes the counter and generates an update of the registers. Note that the prescaler

counter is cleared too.

654

3210

CNT[7:0]

Bits 7:0 CNT[7:0]: Counter value

654

3210

Reserved

PSC[3:0]

Bits 7:4 Reserved

Bits 3:0 PSC[3:0]: Prescaler value

The prescaler value divides the CK_PSC clock frequency.

The counter clock frequency fCK_CNT is equal to fCK_PSC / 2(PSC[3:0]).

PSC contains the value which will be loaded in the active prescaler register at each update event

(including when the counter is cleared through UG bit of TIM4_EGR register).

This means that an update event must be generated in order that a new prescaler value can be

taken into account.

RM0312 Datasheet(PDF) 169 Page - STMicroelectronics

RM0312 Datasheet(HTML) 169 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL