RFM219SW datasheet(29/35 Pages) ETC2

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RFM219SW

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Rev 1.0 | Page 29/35

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The details of each interrupt are introduced in the registers INTCTL_B,

INTCTL_C and INTCTL_D.

The FIFO_WBYTE is the FIFO write-byte strobe that pulses up when

each byte is filled into the FIFO. Because it is a pulse, It cannot be seen

in the INTCTL_C register which reflects the interrupt flags.

3:0

r/w

INT1_CTL<3:0>

This allows the user to select which interrupt is observable on the INT1.

The interrupt mapping is identical to that of the INT2.

Table 20. INTCTL_B

Bit

Bit Name

Descriptions

0: Keep the sleep timer timeout interrupt (default).

INTCTL_B

[1]

(0x42)

Note:

SL_TMO_CLR

RX_TMO_CLR

RSSI_VLD_CLR

PREAM_PS_CLR

SYNC_PS_CLR

NODE_PS_CLR

CRC_PS_CLR

PKT_DONE_CLR

1: Clear the sleep timer timeout interrupt.

0: Keep the receive timer timeout interrupt (default).

1: Clear the receive timer timeout interrupt.

0: Keep the RSSI valid interrupt (default).

1: Clear the RSSI valid interrupt.

0: Keep the preamble detection pass interrupt (default).

1: Clear the preamble detection pass interrupt.

0: Keep the sync word detection pass interrupt (default).

1: Clear the sync word detection pass interrupt.

0: Keep the node ID detection pass interrupt (default).

1: Clear the node ID detection pass interrupt.

0: Keep the CRC validation pass interrupt (default).

1: Clear the CRC validation pass interrupt.

0: Keep the packet receive finish interrupt (default).

1: Clear the packet receive finish interrupt.

[1]. Every bit in this register only takes effect in STBY, TUNE, RX and EEPROM state.

Table 21. INTCTL_C

Bit

Bit Name

Descriptions

INTCTL_C

(0x43)

SL_TMO_FLG

This interrupt is generated when the sleep timer is turned on and the

SL_TMO_EN is set to 1. The flag goes high at the sleep timer timeout. It

can be cleared by setting the SL_TMO_CLR to 1.

RX_TMO_FLG

This interrupt is generated when the receive timer is turned on and the

RX_TMO_EN is set to 1. The flag goes high at the receive timer timeout.

It can be cleared by setting the RX_TMO_CLR to 1.

RSSI_VLD_FLG

This interrupt is generated when (G)FSK demodulation is used and the

RSSI_VLD_EN is set to 1. The flag goes high when the RSSI exceeds

the FSK Trigger Threshold. It can be cleared by setting the

RSSI_VLD_CLR to 1.

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