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GP2021 Datasheet(PDF) 19 Page - Mitel Networks Corporation |
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GP2021 Datasheet(HTML) 19 Page - Mitel Networks Corporation |
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19 / 62 page ![]() 19 GP2021 Fig.17 ROM (1 wait state) and EEPROM/spare (2+1wait states) Read Cycles MCLK NOTE: NRW, NMREQ and DBE are assumed to be Low 20MHz INTERNAL CLOCK ARM_ALE NEEPROM NROM NRD D<15:0> A<22:20>, A<9:0> Fig.18 EEPROM (or Spare) Write Cycle MCLK NOTE: NBW and NRW are assumed to be High for this cycle 20MHz INTERNAL CLOCK ARM_ALE A<22:20>, A<9:0> NEEPROM NW<3:0> DBE D<15:0> |
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