GP2021 datasheet(37/62 Pages) MITEL

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GP2021

To find the duty cycle of the MAG signal, channel 11 is used.

The In–phase accumulator CH11_I_PROMPT will add –3 for

each MAG sample at High and will add –1 for each MAG

sample at Low. If the duty cycle is correct (30%), the sum will

be: –1.6 * (Number of samples) plus an allowance for the

imbalance of sampling at the beginning and end of the

integration period. The duty cycle may be calculated as

follows:

N = Total No of samples in integration period.

N MAG3 = Total No of samples for which MAG was

High

N MAG1 = Total number of samples for which MAG was

Low

ACC11 = Total value in the CH11_I_PROMPT

accumulator, as read after a DUMP.

N = N MAG3 + N MAG1 ,

ACC11 = –3 * N MAG3 –N MAG1

MAG duty cycle, Rm = Nmag3 / N = – (N + ACC11) / 2N

(nominally 0·30).

TM_TEST: When High this bit puts all the Tracking Modules

into a test mode, where it is possible to write to all

CHx_CARRIER_CYCLE_COUNTERs

and

all

CHx_CODE_PHASE_COUNTERs.

TEST_SOURCE: When High this bit enables a self–test

generator formed from the CH0 Code Generator. The data

replaces the SIGN0 and MAG0 inputs. It has a chip rate and

phase set by the CH0_CODE_DCO and a carrier frequency

set by the CH0_CARRIER_DCO. The code is set by writing

the appropriate start value into the CH0_SATCNTL register,

and the CH0_SLEW_COUNTER can be programmed to

delay the start of the code generation by a number of half code

chips. The three most significant bits of the Carrier DCO are

decoded to give the SIGN with 50% of Highs and the MAG with

25% of Highs. The sign of the data pattern is set by

TEST_DATA, EXORed with the CH0 C/A code.

TEST_DATA: This bit sets the sign of the modulation of

the test data generated when TEST_SOURCE is set.

TEST_CACODES: When High, the inverted PROMPT

codes for all channels, 0 to 11, are available for output on data

bus bits 0 to 11 and can be seen in parallel by a read to any

CH6 to CH11 read address.

EN_SCANPATH: When High the chip is in scan test

mode, whereby:

DISCIP 1

becomes

SCAN_IN

DISCOP

becomes

SCAN_OUT

MULTI_FN_IO

becomes

SCANCLK

NOPC/NINTELMOT

becomes

SCANSEL

It should be noted that the DISCOP = SCAN_OUT

function

may

over–ridden

the

DISCOP_SELECT_100KHZ function of SYSTEM_SETUP. It

should also be noted that for correct operation the

MULTI_FN_IO pin should be configured as a Discrete or Scan

Clock Input via the IO_CONFIG register.

PATH_SEL<2:0>: To allow for simple factory testing of

the chip, the GP2021 contains six separate scan paths, one

for each of the major counters in the chip. Only one of these

paths may be enabled at any time and the scan path to be used

is selected via the PATH_SEL<2:0> bits as follows:

PATH_SEL<2:0>

Scan Path Selected

000

RTC Counters

001

ACCUM_INT Counter

010

TIC Counter

011

100KHz Output Counter

100

Timemark Pulse Width

Counter

101

PLL_LOCK Filter

Counter

11X

Not Used

TIMEMARK_CONTROL

(Write Address)

Bit

Bit name

15 to 7

not used

6 to 2

FREE_RUN_RATIO

1 FREE_RUN_TIMEMARK

0 ARM_TIMEMARK

The TIMEMARK Generator operates in one of two ways,

either in armed mode, (not related to ARM System Mode) or

free

run

mode.

armed

mode

setting

the

ARM_TIMEMARK bit arms the TIMEMARK generator which

subsequently produces a TIMEMARK output pulse coincident

with the next rising edge of TIC. This then resets the

ARM_TIMEMARK bit ready for a new arming sequence in the

future. Alternatively, the TIMEMARK generator can be used in

free–run mode, by setting the FREE_RUN_TIMEMARK bit

High. This disables the ARM_TIMEMARK bit. In free run mode

a TIMEMARK pulse is produced coincident with the first rising

edge of TIC after the FREE_RUN_TIMEMARK bit has been

set, and then on an integer number of TIC’s determined by the

FREE_RUN_RATIO bits. In free run mode the TIMEMARK

period is:

TIMEMARK Period = (FREE_RUN_RATIO + 1) * TIC Period

(Free run mode)

All the bits of TIMEMARK_CONTROL are cleared to Low

by a Master Reset.

X_DCO_INCR_HIGH

(Write Address)

This register may be used to write the high bits for any

Carrier or Code DCO in any channel. A write to

X_DCO_INCR_HIGH must always be followed by a write to

the appropriate CHx_CARRIER_DCO_INCR_LOW or

CHx_CODE_DCO_INCR_LOW to define the destination and

to complete the action.

Using X_DCO_INCR_HIGH rather than CHx_CARRIER

–_DCO_INCR_HIGH gives a quicker way of loading the whole

DCO’s values because the _LOW write may follow the

X_DCO_INCR HIGH write immediately (without incurring a

300ns wait).

GP2021 Datasheet(PDF) 37 Page - Mitel Networks Corporation

GP2021 Datasheet(HTML) 37 Page - Mitel Networks Corporation

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