CMOS

MT9080B

2-103

28

CS

Chip Select. Active Low input. Selects the device for microport access in connect memory,

data memory, external and shift register modes. Tying CS high will disable output data

drivers (D0-D15o) in all modes except connect memory and shift register modes.

29

DS

Data Strobe. Active low input. Indicates to the SMX that valid data is present on the

microport data bus during a write operation or that the SMX must output data on a read

operation.

In Connect Memory modes, a low level applied to this input during a write operation indicates

to the SMX that valid data is present on the microport data bus. During a read operation the

low going signal indicates to the SMX that it must output data on the microport data bus.

In Data Memory and External modes, when DS is high, the output data bus D0o-D15o will be

disabled. The input data bus D0i-D15i is not affected.

The DS input has no effect on the input and output busses in Counter or Shift Register

modes.

30

R/W

Read/Write Enable. Data is written into the device when R/W is low and read from it when it

is high. This control input is disabled in data memory and shift register modes. It should be

clocked in with the rising edge of CK. The actual read or write operation will be implemented

on the next rising clock edge.

31

DTA

Data Transfer Acknowledge. Open drain output which is pulled low to acknowledge

completion of microport data transfer. On a read of the SMX, DTA low indicates that the SMX

has put valid data on the data bus. On a write, DTA low indicates that the SMX has

completed latching the data in.

32

NC

No Connection.

33

Ground.

34

NC

No Connection.

35

ODE

Output Data Enable. Control input which enables the output data bus. Pulling this input low

will place the data bus in a high impedance state. The level on this pin is latched by a rising

edge of CK. The output drivers will be enabled or disabled with the rising edge in the next

timeslot (see Fig. 24 for applicable timing in different modes).

36

ME

Message Enable. When tied high the data latched in on the address bus is clocked out on

D0o-D15o. When ME is tied low, the contents of the addressed memory location will be

output on the bus. The level on this pin is latched in with the rising edge of the clock. The

actual mode change is implemented on the rising edge in the next timeslot. Refer to Figures

25 and 26 for more timing information.

37

Mx

Mode X. One of three inputs which permit the selection of different operating modes for the

device. Refer to Table 1 for description of various modes.

38

My

Mode Y. See description for pin 37.

39

Mz

Mode Z. See description for pin 37.

40

NC

No Connection.

41, 42

IC

Internal Connection. Leave open for normal operation.

43

Ground.

44

Supply Voltage. +5V.

45

NC

No Connection.

Pin Description

Pin #

Name

Description