USB3370 datasheet(11/75 Pages) MICROCHIP

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 2012 - 2015 Microchip Technology Inc.

DS00001915B-page 11

USB3370

4.3

ULPI Interface Timing

Note 4-6

REFCLK

does not need to be aligned in any way to the ULPI signals.

4.4

Digital IO Pins

TABLE 4-3:

ULPI INTERFACE TIMING

Parameter

Symbol

Conditions

MIN

MAX

Units

60MHz ULPI Output Clock

Note 4-6

Setup time (STP, data in)

TSC, TSD Model-specific REFCLK

5.0

Hold time (STP, data in)

THC, THD Model-specific REFCLK

0.0

Output delay (control out, 8-bit data out)

TDC, TDD Model-specific REFCLK

1.5

60MHz ULPI Input Clock

Setup time (STP, data in)

TSC, TSD 60MHz REFCLK

3ns

Hold time (STP, data in)

THC, THD 60MHz REFCLK

0ns

Output delay (control out, 8-bit data out)

TDC, TDD 60Mhz REFCLK

0.5

6.0

Note:

CLoad = 10pF.

TABLE 4-4:

DIGITAL IO CHARACTERISTICS: RESETB, STP, DIR, NXT, DATA[7:0], AND REFCLK

PINS

Parameter

Symbol

Conditions

MIN

TYP

MAX

Units

Low-Level Input Voltage

VIL

VSS

0.8

High-Level Input Voltage

VIH

0.68 *

VDDIO

High-Level Input Voltage

REFCLK

and RESETB

VIH_REF

0.68 *

VDDIO

VDD33

Low-Level Output Voltage

VOL

IOL = 8mA

0.4

High-Level Output Voltage

VOH

IOH = -8mA

VDDIO -

0.4

Output rise time

TIORISE

CLOAD = 10pF

1.19

Output fall time

TIOFALL

CLOAD = 10pF

1.56

Input Leakage Current

ILI

±10

Pin Capacitance

Cpin

STP

pull-up resistance

RSTP

InterfaceProtectDisable = 0

kΩ

DATA[7:0]

pull-down

resistance

RDATA_PD

ULPI Synchronous Mode

kΩ

CLKOUT

External Drive

VIH_ED

At start-up or following

reset

0.4 *

VDDIO

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