6

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PI6C49019

Rev. B

06/25/13

PI6C49019

Low Power Networking Clock Generator

Byte 1: Control Register

Bit

Description

Type

Power Up Condi-

tion

Output(s) Affected

Notes

7

OE for 33.33/67.33 MHz output

RW

1

33/67M

1 = enabled

0 = disabled

6

33.33/67.33 MHz Select

RW

0

33/67M

0 = 67.33 MHz

1 = 33.33 MHz

5 to 0

Reserved

R

-

-

-

Bit

Description

Type

Power Up Condi-

tion

Output(s) Affected

Notes

7 to 0

Reserved

R

-

-

-

Byte 2: Control Register

Byte 3: Spread Spectrum Control Register

Bit

Description

Type

Power Up

Condition

Output(s)

Affected

Notes

7

Reserved

RW

0

-

-

6

OE for 48 MHz output

RW

0

48M

1 = enabled

0 = disabled

5

OE for 100 MHz

PCI-Express output PCIE3

RW

1

100MHz HCSL

PCI-Express output

PCIE3

1 = enabled

0 = disabled

4

OE for 100 MHz

PCI-Express output PCIE2

RW

1

100MHz HCSL

PCI-Express output

PCIE2

1 = enabled

0 = disabled

3

OE for 19.2 MHz output

RW

0

19M

1 = enabled

0 = disabled

2

OE for 100 MHz

PCI-Express output PCIE1

RW

1

100MHz HCSL

PCI-Express output

PCIE1

1 = enabled

0 = disabled

1

OE for 100 MHz

PCI-Express output PCIE0

RW

1

100 MHz PCI-Express

output PCIE0

1 = enabled

0 = disabled

0

Reserved

R

-

-

-

Byte 0: Bit 6 and Bit 5 Functionality

Bit 6

Bit 5

Description

0

X

1

0

1

1

Enable outputs according to the SMBus default values; SMBus can control each output.

PD_RESET

HW pin/signal = DO NOT CARE

13-0103