VSP1021 datasheet(1/17 Pages) TI

No. de pieza	VSP1021

Descripción Electrónicos	3-V, 10-BIT, 25-MSPS, LOW-POWER AREA CCD ANALOG FRONT END

PDF	17 Pages

Scroll/Zoom	100%

Fabricante Electrónico	TI [Texas Instruments]

Página de inicio	http://www.ti.com

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VSP1021

3V, 10BIT, 25MSPS, LOW POWER

AREA CCD ANALOG FRONT END

SLES016C− FEBRUARY 2002 − REVISED MARCH 2004

1

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

features

D 10-Bit, 25-MSPS, Analog-to-Digital

Converter (ADC)

D Single Power Supply Operation, 2.7 V to

3.3 V

D Low Power: 95 mW at 2.7 V, Power-Down

Mode: 1 mW

D Full-Channel Differential-Nonlinearity Error:

<

±0.5 LSB Typical

D Full-Channel Integral-Nonlinearity Error:

<

±1.5 LSB Typical

D Dual Input Modes: CCD and Video

D Programmable-Gain Amplifier (PGA) With

0-dB to 36-dB Gain Range (0.047 dB/Step)

for CCD Mode, 0-dB to 12-dB Gain Range

(0.047 dB/Step) for Video Mode

D Serial Interface for Register Configuration

D Programmable Black-Level and Offset

Calibration

D Analog Gain Implementation With Specified

No Missing Code, Even At High Gains

D Additional Digital-to-Analog Converters

(DACs) for External Analog Setting

D Internal Reference Voltages

D Programmable Internal-Timing Signal

Delays

D 48-Terminal TQFP Package

applications

D Digital Still Camera

D Digital Camcorder

D Digital Video Camera

description

The VSP1021 device is a highly-integrated monolithic analog-signal processor/digitizer designed to interface

the area charge-coupled-device (CCD) sensors in digital-camera and camcorder applications. The VSP1021

device performs all the analog processing functions necessary to maximize the dynamic range, corrects various

errors associated with the CCD sensor, and then digitizes the results with an on-chip, high-speed ADC. The key

components of the VSP1021 device include:

D Input clamp circuitry and a correlated double sampler (CDS)

D Programmable-gain amplifier (PGA) with 0-dB to 36-dB gain range for CCD mode and 0-dB to 12-dB range

for video mode

D Two internal DACs for automatic or programmable optical-black-level and offset calibration

D 10-bit, 25-MSPS pipeline ADC for CCD mode and a 28-MSPS ADC for video mode

D Parallel data port for easy microprocessor interface and a serial port for configuring internal control registers

D Two additional DACs for external system control

D Internal reference voltages

The VSP1021 device is designed using advanced CMOS process and operates from a single 3-V power supply

with a normal power consumption of just 95 mW, and 1 mW in power-down mode.

High throughput rate, single 3-V operation, very-low-power consumption, and fully-integrated analog-

processing circuitry make the VSP1021 device an ideal CCD and video-signal-processing solution for electronic

video-camcorder applications.

This device is available in a 48-terminal TQFP package and is specified over an operating temperature range

of –20

°C to 75°C.

AVAILABLE OPTIONS

TA

PACKAGE TQFP (PFB)

−20

°C to 75°C

VSP1021PFB

Copyright

 2004, Texas Instruments Incorporated

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

Número de pieza similar - VSP1021

Fabricante Electrónico	No. de pieza	Datasheet	Descripción Electrónicos
Texas Instruments	VSP1021	628Kb / 6P	3-V, 10-BIT,25-MSPS, LOW-POWER AREA CCD ANALOG FRONT END
	VSP1021	308Kb / 7P	3-V 10-BIT, 25-MSPS, LOW-POWER AREA CCD ANALOG FRONT END REVISED MARCH 2004
	VSP1021PFB	628Kb / 6P	3-V, 10-BIT,25-MSPS, LOW-POWER AREA CCD ANALOG FRONT END
	VSP1021PFB	308Kb / 7P	3-V 10-BIT, 25-MSPS, LOW-POWER AREA CCD ANALOG FRONT END REVISED MARCH 2004
	VSP1021PFB.B	308Kb / 7P	3-V 10-BIT, 25-MSPS, LOW-POWER AREA CCD ANALOG FRONT END REVISED MARCH 2004

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