VSP1021

3V, 10BIT, 25MSPS, LOW POWER

AREA CCD ANALOG FRONT END

SLES016C− FEBRUARY 2002 − REVISED MARCH 2004

13

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

CDS/PGA signal processor

In a CCD imaging system, the output from the CCD sensor is differentially fed to the correlated double sampler

(CDS) of the VSP1021 device. The CCD signal is sampled and held during the reset reference interval and the

video signal interval. By subtracting the two resulting voltage levels, the CDS removes low-frequency noise from

the output of the CCD sensor and obtains the voltage difference between the CCD reference level and the video

level of each pixel. Two sample/hold control pulses (SR and SV) are required to perform the CDS function.

The CCD output is capacitively coupled to the VSP1021 device. The CLAMP input clamps the ac-coupling

capacitor to establish the proper dc bias during the dummy pixel interval. The bias at the input to the VSP1021

device is set to 1.2 V. Normally, CLAMP is applied at the sensor’s line rate. A capacitor with a value ten times

larger than that of the input ac-coupling capacitor should be connected between terminal 28 (CLREF) and

AVSS.

The signal is sent to the PGA after completing the CDS function. The PGA gain can be adjusted from 0 to 36 dB

by programming the internal gain register via the serial port. The PGA is digitally controlled with 10-bit resolution

on a linear dB scale, resulting in a 0.047-dB gain step. The gain can be expressed by the following equation:

Gain = PGA code

× 0.047 dB

where the PGA code has a range of 0 to 767.

For example, if the PGA code = 128, then the PGA Gain = 6 dB (a gain of 2).

In CCD mode, users must use the 0−767 range for the PGA-gain code. The gain stays at 36 dB when the code

is from 768 to 1023.

video-mode operation

The VSP1021 device also provides an analog video processing channel that consists of an input clamp, a PGA,

and an ADC. Setting bit D1 (MOD) to 1 in control register 2 enables the video channel. The video signal must

be connected to terminal 31 (PIN) via a 0.1-

µF capacitor as shown in Figure 4.

The video input has its own clamp circuit operated automatically. Around 60 LSB is added to balance the offset

of the output with zero input.

The PGA gain in the video mode can be adjusted from 0 to 12 dB by programming the internal gain register via

the serial port. The PGA is digitally controlled with 10-bit resolution on a linear dB scale, resulting in a 0.047-dB

gain step. The gain can be expressed by the following equation,

Gain = (PGA code−256)

× 0.047 dB

where the PGA code has a range of 256 to 512.

For the video mode, users must utilize the 256 to 512 range for the PGA gain code. The gain code 0−255 must

not be used, and the gain range is from 12 dB to 24 dB for the gain code range of 513 to 767; however, the offset

might be too large for this gain range.

In the video mode, the internal SR and SV delays need to be set to 0.