A25QFO080QL datasheet(4/58 Pages) AMICC

4 / 58 page

A25LQ080 Series

(April, 2016, Version 1.0)

AMIC Technology Corp.

PIN DESCRIPTION

Chip Select ( S )

The SPI Chip Select (

S ) pin enables and disables device

operation. When Chip Select (

S ) is high the device is

deselected and the Serial Data Output (DO, or IO0, IO1, IO2,

IO3) pins are at high impedance. When deselected, the

devices power consumption will be at standby levels unless

an internal erase, program or write status register cycle is in

progress.

When Chip Select (

S ) is brought low the device will be

selected, power consumption will increase to active levels

and instructions can be written to and data read from the

device. After power-up, Chip Select (

S ) must transition from

high to low before a new instruction will be accepted.

Serial Data Input, Output and IOs (DI, DO and IO0, IO1, IO2,

IO3)

The A25LQ080 support standard SPI, Dual SPI and Quad

SPI

operation.

Standard

SPI

instructions

use

the

unidirectional DI (input) pin to serially write instructions,

addresses or data to the device on the rising edge of the

Serial Clock (C) input pin. Standard SPI also uses the

unidirectional DO (output) to read data or status from the

device on the falling edge of Serial Clock (C).

Dual and Quad SPI instruction use the bidirectional IO pins

to serially write instructions, addresses or data to the device

on the rising edge of Serial clock (C) and read data or status

from the device on the falling edge of Serial Clock (C).

Quad SPI instructions require the non-volatile Quad Enable

bit (QE) in Status Register-2 to be set. When QE=1 the Write

Protect (

W ) pin becomes IO2 and Hold ( HOLD ) pin

becomes IO3.

Write Protect (

W )

The Write Protect (

W ) pin can be used to prevent the Status

Status Register’s Block Protect (CMP, SEC, TB, BP2, BP1

and BP0) bits and Status Register Protect (SRP0) bit, a

portion or the entire memory array can be hardware

protected. The Write Protect (

W ) pin is active low.

When the QE bit of Status Register-2 is set for Quad I/O, the

Write Protect (

W ) pin (Hardware Write Protect) function is

not available since this pin is used for IO2. See the Pin

Configuration for Quad I/O operation.

Hold ( HOLD )

The Hold (

HOLD ) pin allows the device to be paused while

it is actively selected. When Hold (

HOLD ) pin is brought low,

while Chip Select (

S ) pin is low, the DO pin will be at high

impedance and signals on the DI and Serial Clock (C) pins

will be ignored (don’t care). When Hold (

HOLD ) pin is

brought high, device operation can resume. The Hold

function can be useful when multiple devices are sharing the

same SPI signals. The Hold (

HOLD ) pin is active low.

When the QE bit of Status Register-2 is set for Quad I/O. the

Hold (

HOLD ) pin function is not available since this pin is

used for IO3. See the Pin Configuration for Quad I/O

operation.

Serial Clock (C)

The SPI Serial Clock Input (C) pin provides the timing for

serial input and output operations.

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