PC87365 datasheet(45/215 Pages) NSC

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2.0 Device Architecture and Configuration (Continued)

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2.9.1

SuperI/O ID Register (SID)

This register contains the identity number of the chip. The PC87365 is identified by the value E5h.

Location:

Index 20h

Type:

2.9.2

SuperI/O Configuration 1 Register (SIOCF1)

Location:

Index 21h

Type:

R/W

Bit

76543210

Name

Chip ID

Reset

11100101

Bit

76543210

Name

Function

Select Lock

Pins

117-127

Function

Select

Number of DMA Wait

States

Number of I/O Wait

States

SW Reset

Global

Device

Enable

Reset

00010001

Bit

Description

Pin Function Select Lock. This bit determines if the bits (located in the SIOCF1, 2, 3, 4, 5, A and B registers)

that select pin functions are read only or read/write. When set to 1, this bit can only be cleared by a hardware

reset.

0: Bits are R/W

1: Bits are RO

Pins 117-127 Function Select.

0: Pins 117-127 function set by SIOCF4 (default)

1: Pins 117-127 are PIRQ3-7, 9, 11-12, 14-15

5-4

Number of DMA Wait States.

Bits

5 4

Number

0 0

Reserved

0 1

Two (default)

1 0

Six

1 1

Twelve

3-2

Number of I/O Wait States.

Bits

3 2

Number

0 0

Zero (default)

0 1

Two

1 0

Six

1 1

Twelve

SW Reset. Read always returns 0.

0: Ignored (default)

1: Resets all the logical devices that are reset by hardware reset (with the exception of the lock bits) and resets

the registers of the SWC, VLM and TMS

Global Device Enable. This bit controls the function enable of all the PC87365 logical devices, except System

Wake-Up Control (SWC). With the exception of SWC, it allows all logical devices to be disabled simultaneously

by writing to a single bit.

0: All logical devices in the PC87365 are disabled, except SWC, VLM and TMS

1: Each logical device is enabled according to its Activate register (Index 30h) (default)

PC87365 Datasheet(PDF) 45 Page - National Semiconductor (TI)

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