| Motor de Búsqueda de Datasheet de Componentes Electrónicos |
|
PC87365 Datasheet(PDF) 78 Page - National Semiconductor (TI) |
|
|
|
|||||||||||||||||||||||||||||
PC87365 Datasheet(HTML) 78 Page - National Semiconductor (TI) |
|
78 / 215 page ![]() 2.0 Device Architecture and Configuration (Continued) 78 www.national.com 2.19 WATCHDOG TIMER (WDT) CONFIGURATION 2.19.1 Logical Device 10 (WDT) Configuration Table 33 lists the configuration registers that affect the WATCHDOG Timer. Only the last register (F0h) is described here. See Sections 2.2.3 and 2.2.4 for a detailed description of the others. Table 33. WDT Configuration Registers 2.19.2 WATCHDOG Timer Configuration Register This register is reset by hardware to 02h. Location: Index F0h Type: R/W Index Configuration Register or Action Type Reset 30h Activate. When bit 0 is cleared, the registers of this logical device are not accessible. R/W 00h 60h Base Address MSB register. R/W 00h 61h Base Address LSB register. Bits 1 and 0 (for A1 and A0) are read only, 00b. R/W 00h 70h Interrupt Number (for routing the WDO signal) and Wake-Up on IRQ Enable register (see note, p. 35). R/W 00h 71h Interrupt Type. Bit 1 is read/write. Other bits are read only. R/W 03h 74h Report no DMA assignment. RO 04h 75h Report no DMA assignment. RO 04h F0h WATCHDOG Timer Configuration register. R/W 02h Bit 76543210 Name Reserved Output Type Internal Pull-Up Enable Power Mode Control TRI-STATE Control Reset 00000010 Bit Description 7-4 Reserved. 3 Output Type. This bit controls the buffer type (open-drain or push-pull) of the WDO pin. 0: Open-drain (default) 1: Push-pull 2 Internal Pull-Up Enable. This bit controls the internal pull-up resistor on the WDO pin. 0: Disabled (default) 1: Enabled 1 Power Mode Control. 0: Low power mode: WATCHDOG Timer clock disabled. WDO output signal is set to 1. Registers are accessible and maintained (unlike Active bit in Index 30h that also prevents access to WATCHDOG Timer registers). 1: Normal power mode: WATCHDOG Timer clock enabled. WATCHDOG Timer is functional when the logical device is active (default). 0 TRI-STATE Control. When enabled and the device is inactive, the logical device output pins are in TRI-STATE. 0: Disabled (default) 1: Enabled |
|
Enlace URL |
| ¿ALLDATASHEET es útil para Ud.? [ DONATE ] |
Todo acerca de Alldatasheet | Publicidad | Contáctenos | Política de Privacidad | Enlace a la hoja de datos | Intercambio de Enlaces | Lista de Fabricantes All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |