SPT

3

3/21/97

SPT9687

ELECTRICAL SPECIFICATIONS

TEST

TEST

SPT9687

PARAMETERS

CONDITIONS

LEVEL

MIN

TYP

MAX

UNITS

Latch to Output Delay

50 mV OD

IV

3

ns

Latch Pulse Width

V

2

ns

Latch Hold Time

IV

0.5

ns

Rise Time

20% to 80%

V

1.2

ns

Fall Time

20% to 80%

V

1.2

ns

Figure 1 - Timing Diagram

50%

VREF ± VOS

50%

50%

t

t

tpL

pLOL

pLOH

DIFFERENTIAL

INPUT VOLTAGE

OUTPUT Q

OUTPUT Q

LATCH ENABLE

LATCH ENABLE

V

OD

The set-up and hold times are a measure of the time required for an input signal to propagate through the

TEST LEVEL CODES

All electrical characteristics are subject to the

following conditions:

All parameters having min/max specifications

are guaranteed. The Test Level column indi-

cates the specific device testing actually per-

formed during production and Quality Assur-

ance inspection. Any blank section in the data

column indicates that the specification is not

tested at the specified condition.

Unless otherwise noted, all tests are pulsed

TEST PROCEDURE

100% production tested at the specified temperature.

tested at the specified temperatures.

QA sample tested only at the specified temperatures.

Parameter is guaranteed (but not tested) by design

and characterization data.

Parameter is a typical value for information purposes

only.

guaranteed over specified temperature range.

TEST LEVEL

I

II

III

IV

V

VI