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STGAP1ASTR Datasheet(PDF) 12 Page - STMicroelectronics |
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STGAP1ASTR Datasheet(HTML) 12 Page - STMicroelectronics |
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12 / 70 page ![]() Electrical data STGAP1AS 12/70 DocID029344 Rev 2 3.2 Thermal data 3.3 Recommended operating conditions Table 3. Thermal data Symbol Parameter Value Unit Rth(JA) Thermal resistance junction to ambient(1) 65 °C/W 1. The STGAP1AS mounted on the EVALSTGAP1AS rev 2.0 board (two-layer FR4 PCB). Table 4. Recommended operating conditions Symbol Pin Parameter Test condition Min. Max. Unit VH 17 Positive supply voltage (VH vs. GNDISO) -4.50(1) 36 V VL 14, 23 Negative supply voltage (VL vs. GNDISO) - GNDISO - 10 GNDISO(2) V VHL - Differential supply voltage (VH vs. VL) -- 36 V VDD 7 Low voltage section power supply voltage vs. GND - 4.50 5.50 V VREG 6 Low voltage section internal regulator voltage vs. GND (3) 3.3 ± 5% V VLOGIC 2, 3, 4, 5, 8, 9, 11 Logic pins voltage vs. GND - - (VDD, 5)min V ASC 24 ASC pin voltage - GNDISO (VH, 15)min V VDESATth 18 Desaturation protection threshold DESAT enabled - VH - 1.50 V fSW Maximum switching frequency(4) *- 150 kHz 1. When UVLO is enabled this value is VHon,max. 2. When UVLO is enabled this value is VLon,min. 3. When VDD is connected to the VREG pin (refer to Section 6 on page 22). 4. Actual limit depends on power dissipation constraints. |
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