STGAP1ASTR datasheet(22/70 Pages) STMICROELECTRONICS

22 / 70 page

Logic supply management

STGAP1AS

22/70

DocID029344 Rev 2

Logic supply management

6.1

Low voltage section voltage regulator

The device integrates in the low voltage section a linear voltage regulator that can be used

to obtain the 3.3 V logic core supply voltage from an external 5 V supply voltage. If an

external 3.3 V supply voltage is available the VDD and VREG have to be shorted as shown

in Figure 3. The logic IOs are referred to the VDD voltage (see Table 6 on page 14 for

details).

Figure 3. Low voltage section 3.3 V voltage regulator

Undervoltage protection is available on the VDD supply pin (disabled by default).

When the VDD voltage goes below the VDDoff threshold the device and its outputs goes in

“safe state” (see Section 6.3) and the UVLOD status flag is forced low. Once the protection

is triggered, the UVLOD flag is latched and the device remains in “safe state” until the

UVLOD flag is not released. See Section 7.11 on page 35 for indication on how the failure

flags can be released.

This protection can be enabled writing the UVLOD_EN bit of the CFG1 register (disabled by

default).

Overvoltage protection is available on the VDD supply pin.

When the VDD voltage goes over the OVVDDoff threshold the device and its outputs goes in

“safe state” and the OVLOD status flag is set. The device remains in “safe state” and the

OVLOD flag is latched, see Section 7.11 for indication on how the failure flags can be

released.

VREG

VDD

+5V

LDO

Reg

4.7 µF

100 nF

VDD from +5 V power supply

VREG

VDD

+3.3V

LDO

Reg

4.7 µF

100 nF

VDD from +3.3 V power supply

STGAP1ASTR Datasheet(PDF) 22 Page - STMicroelectronics

STGAP1ASTR Datasheet(HTML) 22 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70

Datasheet Descarga

Enlace URL