THC63LVDR84C_Rev.1.20_E

Copyright©2016 THine Electronics, Inc.

7

THine Electronics, Inc.

Security E

Switching Characteristics

Over recommended operating supply and temperature range unless otherwise specified

Symbol

Parameter

Min

Typ*

Max

Unit

RCLK and CLKOUT Transition Time

8.92

T

125

ns

LVCMOS CLKOUT High Time

-

T/2

-

ns

LVCMOS CLKOUT Low Time

-

T/2

-

ns

RCLK IN to CLKOUT Delay

-

(3/14+3)×T

-

ns

LVCMOS Data Setup to CLKOUT

0.35×T - 0.3

-

-

ns

LVCMOS Data Hold from CLKOUT

0.45×T - 1.6

-

-

ns

LVCMOS Low to High Transition Time

-

0.7

1.0

ns

LVCMOS High to Low Transition Time

-

0.7

1.0

ns

LVDS Receiver Skew Margin

PCLK=65MHz

-0.55

-

0.55

ns

PCLK=112MHz

-0.25

-

0.25

LVDS Input Data Position0

0.0

ns

LVDS Input Data Position1

T/7

ns

LVDS Input Data Position2

2T/7

ns

LVDS Input Data Position3

3T/7

ns

LVDS Input Data Position4

4T/7

ns

LVDS Input Data Position5

5T/7

ns

LVDS Input Data Position6

6T/7

ns

Phase Lock Loop Set

-

-

10.0

ms

*Typ values are at the conditions of VCC33=3.3V and Ta = +25ºC

Table 8. LVCMOS & LVDS Receiver AC Specifications