LP2975 datasheet(16/19 Pages) NSC

16 / 19 page

Application Hints (Continued)

To estimate the total phase margin, the individual phase shift

contributions of each pole and zero will be calculated assum-

ing f

p = 200 Hz, fz = 5 kHz, fzf = 10 kHz, fpf = 40 kHz,

c = 50 kHz, and fpg= 100 kHz:

Controller pole shift = −90˚

p shift = −arctan (50k/200) = −90˚

z shift = arctan (50k/5k) = +84˚

zf shift = arctan (50k/100k) = +79˚

pf shift = −arctan (50k/40k) = −51˚

pg shift = −arctan (50k/100k) = −27˚

Summing the six numbers, the estimate for the total phase

shift is −95˚, which corresponds to a phase margin of 85˚

(a 27˚ improvement over the same application without the

feed-forward capacitor).

For this reason, a feed-forward capacitor is recommended in

all applications. Although not always required, the added

phase margin typically gives faster settling times and pro-

vides some design guard band against C

OUT and ESR varia-

tions with temperature.

CAUSES AND CURES OF OSCILLATIONS

The most common cause of oscillations in an LDO applica-

tion is the output capacitor ESR. If the ESR is too high or too

low, the zero (f

z) does not provide enough phase lead.

HIGH ESR: To illustrate the effect of an output capacitor with

high ESR, the previous example will be repeated except that

the ESR will be increased by a factor of 20X. This will cause

the frequency of the zero f

z to decrease by 20X, which

moves it from 5 kHz down to 250 Hz (see graph

HIGH ESR

UNSTABLE WITHOUT FEED-FORWARD).

As shown, moving the location of f

z lower in frequency ex-

tends the bandwidth, pushing the crossover frequency f

c out

to about 200 kHz. In viewing the plot, it can be seen that f

and f

z essentially cancel out, leaving only the controller pole

and f

pg. However, since fpg now occurs well before fc, it will

cause enough phase shift to leave very little phase margin.

This application would either oscillate continuously or be

marginally stable (meaning it would exhibit severe ringing on

transient steps).

This can be improved by adding a feed-forward capacitor C

which adds a zero (f

zf) and a pole (fpf) to the gain plot (see

graph

HIGH ESR CORRECTED WITH FEED-FORWARD).

In this case, C

F is selected to place fzf at about the same fre-

quency as f

pg (essentially cancelling out the phase shift due

to f

pg). Assuming the added pole fpf is near or beyond the fc

frequency, it will add < 45˚ of phase lag, leaving a phase

margin of > 45˚ (adequate for good stability).

LOW ESR: To illustrate how an output capacitor with low

ESR can cause an LDO regulator to oscillate, the same ex-

ample will be shown except that the ESR will be reduced suf-

ficiently to increase the original f

z from 5 kHz to 50 kHz.

The plot now shows (see graph

LOW ESR UNSTABLE

WITHOUT FEED-FORWARD) that the crossover frequency

c has moved down to about 8 kHz. Since fz is 6X fc, it means

that the zero f

z can only provide about 9˚ of phase lead at fc,

which is not sufficient for stability.

Improved Phase Margin with Feed-Forward

DS100034-28

High ESR Unstable without Feed-Forward

DS100034-29

High ESR Corrected with Feed-Forward

DS100034-31

LP2975 Datasheet(PDF) 16 Page - National Semiconductor (TI)

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