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ADE7754AR Datasheet(PDF) 40 Page - Analog Devices |
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ADE7754AR Datasheet(HTML) 40 Page - Analog Devices |
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40 / 44 page ![]() REV. PrG 01/03 PRELIMINARY TECHNICAL DATA ADE7754 – 40 – Measurement Mode Register (0Bh) The configuration of the period and Peak measurements made by the ADE7754 are defined by writing to the MMODE register. Table XII below summarizes the functionality of each bit in the MMODE register . Table XII MMODE Register Bit Bit Default Location Mnemonic Value Description 0-1 PERDSEL 0 These bits are used to select the source of the measurement of the voltage line period. bit 1 bit 0 Source 0 0 Phase A 0 1 Phase B 1 0 Phase C 1 1 Reserved 2-3 PEAKSEL 0 These bits select the line voltage and current phase used for the PEAK detection. If the selected line voltage is above the level defined in the PKVLVL register, the PKV flag in the Interrupt Status register is set. If the selected current input is above the level defined in the PKILVL register, the PKI flag in the Interrupt Status register is set. bit 3 bit 2 Source 0 0 Phase A 0 1 Phase B 1 0 Phase C 1 1 Reserved 4-6 ZXSEL 7 These bits select the phases used for counting the number of zero crossing in the Line Active and Apparent accumulation modes as well as enabling these phases for the Zero- Crossing Time out detection, Zero-crossing, Period measurement and SAG detection. bit 4, 5 and 6 select Phase A, Phase B and Phase C respectively. 7 Reserved Waveform Mode Register (0Ch) The Waveform sampling mode of the ADE7754 is defined by writing to the WAVMODE register. Table XIII below summarizes the functionality of each bit in the WAVMODE register . Table XIII WAVMODE Register Bit Bit Default Location Mnemonic Value Description 0-2 WAVSEL 0 These bits are used to select the source of the Waveform sample bit 2 bit 1 bit 0 Source 0 0 0 Voltage Phase A 0 0 1 Voltage Phase B 0 1 0 Voltage Phase C 0 1 1 Current Phase A 1 0 0 Current Phase B 1 0 1 Current Phase C 1 1 0 or 1 Reserved 3-4 DTRT 0 These bits are used to select the Waveform sampling update rate bit 4 bit 3 Update rate 0 0 26.0ksps (CLKIN/3/128) 0 1 13.0ksps (CLKIN/3/256) 1 0 6.5ksps (CLKIN/3/512) 1 1 3.3ksps (CLKIN/3/1024) 5 LVARSEL 0 This bit is used to enable the accumulation of the Line VAR energy into the LAENERGY register and of the Line Active Energy into the LVAENERGY register. |
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