AT89C51CC03U-RDTIM datasheet(50/195 Pages) ATMEL

50 / 195 page

AT89C51CC03

4182I–CAN–06/05

order. The page address of the last address loaded in the column latches will be used

for the whole page.

When programming is launched, an automatic erase of the locations loaded in the col-

umn latches is first performed, then programming is effectively done. Thus no page or

block erase is needed and only the loaded data are programmed in the corresponding

page

Notes: 1. : If no bytes are written in the column latches the SEQERR bit in the FSTA register

will be set.

2. When a flash write sequence is in progress (FBUSY is set) a write sequence to the

column latches will be ignored and the content of the column latches at the time of

the launch write sequence will be preserved.

3. MOVX @DPTR, A instruction must be used to load the column latches. Never use

MOVX @Ri, A instructions.

4. When a programming sequence is launched, Flash bytes corresponding to activated

bytes in the column latches are first erased then the bytes in the column latches are

copied into the Flash bytes. Flash bytes corresponding to bytes in the column latches

not activated (not loaded during the load column latches sequence) will not be erased

and written.

The following procedure is used to load the column latches and is summarized in

Figure 25:

•

Save and Disable interrupt and map the column latch space by setting FPS bit.

•

Load the DPTR with the address to load.

•

Load Accumulator register with the data to load.

•

Execute the MOVX @DPTR, A instruction.

•

If needed loop the three last instructions until the page is completely loaded.

•

unmap the column latch.

•

Restore Interrupt

AT89C51CC03U-RDTIM Datasheet(PDF) 50 Page - ATMEL Corporation