PC87309VLJ datasheet(109/192 Pages) NSC

109 / 192 page

Enhanced Serial Port with IR -UART2 (Logical Device 2)

109

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0: Disable Receiver High-Data-Level and RX_FIFO

Time-Out interrupts (Default).

1: Enable Receiver High-Data-Level and RX_FIFO

Time-Out interrupts.

Bit 1 - Transmitter Low-Data-Level Interrupt Enable

(TXLDL_IE)

Setting this bit enables interrupts on Transmitter Low

Data-Level-events (EIR Bits 3-0 are 0010. See Table

5-3 on page 110).

0: Disable Transmitter Low-Data-Level Interrupts (De-

fault).

1: Enable Transmitter Low-Data-Level Interrupts.

Bit 2 - Link Status Interrupt Enable (LS_IE)

Setting this bit enables interrupts on Link Status events.

(EIR Bits 3-0 are 0110. See Table 5-3 on page 110).

0: Disable Link Status Interrupts (LS_EV) (Default).

1: Enable Link Status Interrupts (LS_EV).

Bit 3 - Modem Status Interrupt Enable (MS_IE)

Setting this bit enables the interrupts on Modem Status

events. (EIR Bits 3-0 are 0000. See Table 5-3 on page

110).

0 - Disable Modem Status Interrupts (MS_EV) (De-

fault).

1: Enable Modem Status Interrupts (MS_EV).

Bits 7-4- Reserved

These bits are reserved.

Interrupt Enable Register (IER), in the Extended Modes

of UART, Sharp-IR and SIR

See the bitmap of the Interrupt Enable Register in these

modes.

Bit 0 - Receiver High-Data-Level Interrupt Enable

(RXHDL_IE)

Setting this bit enables interrupts when the RX_FIFO is

equal to or above the RX_FIFO threshold level, or an

RX_FIFO time out occurs.

0: Disable Receiver Data Ready interrupt. (Default)

1: Enable Receiver Data Ready interrupt.

Bit 1 - Transmitter Low-Data-Level Interrupt Enable

(TXLDL_IE)

Setting this bit enables interrupts when the TX_FIFO is

below the threshold level or the Transmitter Holding

0: Disable Transmitter Low-Data-Level Interrupts (De-

fault).

1: Enable Transmitter Low-Data-Level Interrupts.

Bit 2 - Link Status Interrupt Enable (LS_IE)

Setting this bit enables interrupts on Link Status events.

0: Disable Link Status Interrupts (LS_EV) (Default)

1: Enable Link Status Interrupts (LS_EV).

Bit 3 - Modem Status Interrupt Enable (MS_IE)

Setting this bit enables the interrupts on Modem Status

events.

0: Disable Modem Status Interrupts (MS_EV) (De-

fault)

1: Enable Modem Status Interrupts (MS_EV).

Bit 4 - DMA Interrupt Enable (DMA_IE)

Setting this bit enables the interrupt on terminal count

when the DMA is enabled.

0: Disable DMA terminal count interrupt (Default)

1: Enable DMA terminal count interrupt.

Bit 5 - Transmitter Empty Interrupt Enable (TXEMP_IE)

Setting this bit enables interrupt generation if the trans-

mitter and TX_FIFO become empty.

0: Disable Transmitter Empty interrupts (Default)

1: Enable Transmitter Empty interrupts.

Bits 7,6 - Reserved

Reserved.

Interrupt Enable Register (IER), Consumer-IR Mode

See the bitmap of the Interrupt Enable Register (IER) in this

mode.

Bit 1-0 -

Same as in the Extended Modes of UART and Sharp-IR

(See previous sections).

76543210

Reset

Required

MS_IE

DMA_IE

TXEMP_IE

Reserved

Interrupt Enable

RXHDL_IE

TXLDL_IE

LS_IE

Bank 0,

Extended Mode of UART, Sharp-IR and SIR

Offset 01h

76543210

Reset

Required

Interrupt Enable

Bank 0,

LS_IE or TXUR_IE

DMA_IE

TXEMP_IE

Reserved

RXHDL_IE

TXLDL_IE

MS_IE

Offset 01h

Consumer-IR Mode

PC87309VLJ Datasheet(PDF) 109 Page - National Semiconductor (TI)

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