Application details

L6739

22/30

DocID026384 Rev 1

the same high current trace on more than one PCB layer reduces the parasitic resistance

associated to that connection.

inductance and resistance associated to the copper trace, also adding extra decoupling

capacitors along the way to the load when this results in being far from the bulk capacitors

bank.

Remote sense connection must be routed as parallel nets from the FBG/VSEN pins to the

load in order to avoid the pickup of any common mode noise. Connecting these pins in

points far from the load causes a non-optimum load regulation, increasing output tolerance.

Locate current reading components close to the device. The PCB traces connecting the

reading point must use dedicated nets, routed as parallel traces in order to avoid the pickup

of any common mode noise. It's also important, to avoid any offset in the measurement and,

to get a better precision, to connect the traces as close as possible to the sensing elements.

CSN line to allow higher layout flexibility.

Figure 11. Power connections (heavy lines)

Gate traces and phase trace must be sized according to the driver RMS current delivered to

the power MOSFET. The device robustness allows the managing of applications with the

power section far from the controller without losing performance. However, when possible, it

is recommended to minimize the distance between the controller and power section.

Small signal components and connections to critical nodes of the application, as well as

bypass capacitors for the device supply, are also important. Locate the bypass capacitor

(VCC and bootstrap capacitor) and feedback compensation components as close to the

device as practical.