SPC560P34L1 datasheet(20/103 Pages) STMICROELECTRONICS

20 / 103 page

Introduction

SPC560P34L1, SPC560P34L3, SPC560P40L1, SPC560P40L3

20/103

Doc ID 16100 Rev 7

platform memory errors reported by error-correcting codes and/or generic access error

information for certain processor cores.

The Error Correction Status Module supports a number of miscellaneous control functions

for the platform. The ECSM includes these features:

●

Registers for capturing information on platform memory errors if error-correcting codes

(ECC) are implemented

●

For test purposes, optional registers to specify the generation of double-bit memory

errors are enabled on the SPC560P34/SPC560P40.

The sources of the ECC errors are:

●

Flash memory

●

SRAM

1.5.19

Peripheral bridge (PBRIDGE)

The PBRIDGE implements the following features:

●

Duplicated periphery

●

Master access privilege level per peripheral (per master: read access enable; write

access enable)

●

Write buffering for peripherals

●

Checker applied on PBRIDGE output toward periphery

●

Byte endianess swap capability

1.5.20

Controller area network (FlexCAN)

The SPC560P34/SPC560P40 MCU contains one controller area network (FlexCAN)

module. This module is a communication controller implementing the CAN protocol

according to Bosch Specification version 2.0B. The CAN protocol was designed to be used

primarily as a vehicle serial data bus, meeting the specific requirements of this field: real-

time processing, reliable operation in the EMI environment of a vehicle, cost-effectiveness

and required bandwidth. The FlexCAN module contains 32 message buffers.

SPC560P34L1 Datasheet(PDF) 20 Page - STMicroelectronics