ST7MC1K2 datasheet(77/371 Pages) STMICROELECTRONICS

No. de pieza	ST7MC1K2

Descripción Electrónicos	Clock, reset and supply management

PDF	371 Pages

Scroll/Zoom	100%

Fabricante Electrónico	STMICROELECTRONICS [STMicroelectronics]

Página de inicio	http://www.st.com

Logo

77 / 371 page

Obsolete

Product(s)

- Obsolete

Product(s)

ST7MC1K2-Auto, ST7MC1K6-Auto, ST7MC2S4-Auto, ST7MC2S6-Auto

Power saving modes

77/371

Figure 27.

Halt mode flowchart

WDGHALT is an option bit. See option byte section for more details.

Peripherals clocked with an external clock source can still be active.

Only some specific interrupts can exit the MCU from Halt mode (such as external interrupt). Refer to

Table 22: Interrupt mapping on page 70 for more details.

Before servicing an interrupt, the CC register is pushed on the stack. The I[1:0] bits of the CC register are

set to the current software priority level of the interrupt routine and recovered when the CC register is

popped.

HALT instruction

Reset

Interrupt(3)

Fetch reset vector or

service interrupt

256 or 4096 CPU clock

Watchdog

Enable

Disable

WDGHALT(1)

Watchdog

reset

(MCCSR.OIE = 0)

cycle delay

CPU

Oscillator

Peripherals(2)

I[1:0] bits

Off

CPU

Oscillator

Peripherals

I[1:0] bits

Off

XX(4)

CPU

Oscillator

Peripherals

I[1:0] bits

XX(4)

Obsolete

Product(s)

- Obsolete

Product(s)

ST7MC1K2 Datasheet(PDF) 77 Page - STMicroelectronics

ST7MC1K2 Datasheet(HTML) 77 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL