ST7MC1K2 datasheet(45/371 Pages) STMICROELECTRONICS

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6.4

Reset sequence manager (RSM)

6.4.1

Introduction

The reset sequence manager includes three reset sources are shown in Figure 11.

●

External RESET source pulse

●

Internal LVD reset (low voltage detection)

●

internal watchdog reset

Note:

A reset can also be triggered following the detection of an illegal opcode or prebyte code.

Refer to Section 11.2.2 on page 309 for further details.

These sources act on the RESET pin and it is always kept low during the delay phase.

The reset service routine vector is fixed at addresses FFFEh-FFFFh in the ST7 memory

map.

The basic reset sequence consists of three phases as shown in Figure 10.

●

Active phase depending on the reset source

●

256 or 4096 CPU clock cycle delay (selected by option byte)

●

Reset vector fetch

Caution:

When the ST7 is unprogrammed or fully erased, the Flash is blank and the reset vector is

not programmed. For this reason, it is recommended to keep the RESET pin in low state

until programming mode is entered, in order to avoid unwanted behavior.

The 256 or 4096 CPU clock cycle delay allows the oscillator to stabilize and ensures that

recovery has taken place from the reset state. The shorter or longer clock cycle delay

should be selected by option byte to correspond to the stabilization time of the external

oscillator used in the application.

The reset vector fetch phase duration is 2 clock cycles.

Figure 10.

Reset sequence phases

6.4.2

Asynchronous external RESET pin

The RESET pin is both an input and an open-drain output with integrated RON weak pull-up

resistor. This pull-up has no fixed value but varies in accordance with the input voltage. It

can be pulled low by external circuitry to reset the device. See Section 12: Electrical

characteristics for more details.

A reset signal originating from an external source must have a duration of at least th(RSTL)in

in order to be recognized (see Figure 12). This detection is asynchronous and therefore the

MCU can enter reset state even in Halt mode.

Reset

Active phase

Internal reset

256 or 4096 clock cycles

vector

Fetch

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