ST10F296 datasheet(84/346 Pages) STMICROELECTRONICS

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The bootstrap loader

ST10F296E

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To achieve this, the PT0 value is divided into ranges of 1450 ticks. In the bootstrap

algorithm, PT0 is divided by 1451 and the result gives the BRP value.3

This calculated BRP value is then divided into PT0 to give the ‘1+ Tseg1 + Tseg2’ value. A

table is then made to set the values for Tseg1 and Tseg2 according to the ‘1+ Tseg1 +

Tseg2’ value. The Tseg1 and Tseg2 values are chosen to reach a sample point between

70% and 80% of the bit time.

During the calculation of ‘1+ Tseg1 + Tseg2’, an error, e2, can be introduced. The maximum

value of this error is 1 time quantum.

To compensate for any possible errors on the bit rate, the (re)synchronization jump width is

fixed to two time quanta.

6.4.6

How to compute the baud rate error

An example of the baud rate error computation is as follows:

Conditions:

●

CPU frequency: 20 MHz

●

Target bit rate: 1 Mbit/s

The content of the PTO timer for bit 29 is given in Equation 6:

Equation 6

Therefore:

574 < [PT0] < 586

This gives:

–BRP = 0

–

tq = 100 ns

Computation of 1 + Tseg1 + Tseg2 considering Equation 4 is given in Equation 7:

Equation 7

In the algorithm, a rounding to the superior value is made if the remainder of the division is

greater than half of the divisor. This would have been the case above, if the PT0 content was

574. Thus in this example, 1+Tseg1+Tseg2 = 10, giving a bit time of exactly 1µs => no error

in bit rate.

Note:

In most cases (24 MHz, 32 MHz, and 40 MHz of CPU frequency and 125, 250, 500 or

1Mbyte/s of bit rate) there is no error. However, it is better to check the error with real

application parameters.

The content of the bit timing register is : 0x1640. This gives a sample point of 80%.

Note:

The (re)synchronization jump width is fixed to 2 time quanta.

PT0

[

]

CPU

BitRate

()

⁄

6110

⁄

580

574

---------- Tseg1

Tseg2

586

----------10

≤

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