ST10F296 datasheet(118/346 Pages) STMICROELECTRONICS

118 / 346 page

Obsolete

Product(s)

- Obsolete

Product(s)

Parallel ports

ST10F296E

118/346

Parallel ports

The ST10F296E MCU provides up to 143 I/O lines with programmable features. The MCU is

therefore very flexible for a wide range of applications.

The ST10F296E has 11 groups of I/O lines organized as follows:

●

Port 0 is a two-time, 8-bit port named P0L (low is the least significant byte) and P0H

(high is the most significant byte)

●

Port 1 is a two-time, 8-bit port named P1L and P1H

●

Port 2 is a 16-bit port

●

Port 3 is a 15-bit port (P3.14 line is not implemented)

●

Port 4 is an 8-bit port

●

Port 5 is a 16-bit input only port

●

Port 6, Port 7 and Port 8 are 8-bit ports

●

XPort 9 is a 16-bit general purpose port

●

XPort 10 is a 16-bit input only port

These ports may be used as general purpose bidirectional input or output, software

controlled with dedicated registers.

For example the output drivers of seven of the ports (2, 3, 4, 6, 7, 8, and 9) can be

configured (bit-wise) for push-pull or open-drain operation using the ODPx registers (and the

XODP9 register for XPort 9).

The input threshold levels are programmable (TTL/CMOS) for all ports. The logic level of a

pin is clocked into the input latch once per state time, regardless of whether the port is

configured for input or output. The threshold is selected with PICON and XPICON registers

control bits.

A write operation to a port pin configured as an input causes the value to be written into the

port output latch, while a read operation returns the latched state of the pin itself. A read-

modify-write operation reads the value of the pin, modifies it, and writes it back to the output

latch.

Writing to a pin configured as an output (DPx.y = 1) causes the output latch and the pin to

have the written value, since the output buffer is enabled. Reading this pin returns the value

of the output latch. A read-modify-write operation reads the value of the output latch,

modifies it, and writes it back to the output latch, thus also modifying the level at the pin.

I/O lines support an alternate function which is detailed in Section 13.1.4, Section 13.2.2,

Section 13.3.2, and Section 13.4.2.

Note:

The I/O ports XPort 9 and XPort10 are not mapped on the SFR space but on the internal

XBus interface. They are enabled by setting the XPEN bit, bit 2, of the SYSCON register and

bit 11 of the XPERCON register. On the XBus interface, the registers are not bit-

addressable

Obsolete

Product(s)

- Obsolete

Product(s)

ST10F296 Datasheet(PDF) 118 Page - STMicroelectronics

ST10F296 Datasheet(HTML) 118 Page - STMicroelectronics

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Descarga

Enlace URL