NU

REFIN 2

REFIN

1

2

3

4

5

6

7

8

9

2

3

2

2

2

1

2

0

1

9

1

8

1

7

1

6

1

5

PGND

PGND

PGND

PGND

PGND

EN

VREF

TPS51362

www.ti.com

SLUSBB6A – FEBRUARY 2013 – REVISED JUNE 2013

Figure 22. TPS51362 Design Layout

Input capacitors, output capacitors, and the output inductor are the power components and should be placed on

one side of the PCB. Small signal components can be placed on the same side of the PCB with proper ground

isolation or the opposite side with at least one inner ground plane in between, depending on the

system/motherboard design requirement.

All sensitive analog traces and components such as VSNS, GSNS, SLEW, VREF, REFIN and REFIN2 should be

placed away from the high voltage switching node, such as SW and BST to avoid switching noise coupling. Use

internal layer(s) as ground plane(s) and shield feedback traces from power traces.

VSNS can be connected directly to the output voltage sense point at the load device or the bulk capacitor at the

converter side. Connect GSNS to ground return at the general ground plane/layer. VSNS and GSNS can be

used for the purpose of remote sensing across the load device, however, ensure to minimize the routing trace

length to prevent excess noise injection into the sense lines.

In order to effectively remove heat from the package, prepare the thermal land and solder to the package thermal

pad. Wide trace of the component-side copper, connected to this thermal land, helps to dissipate the heat.

Numerous vias (at least 6) with a 0.3-mm diameter connected from the thermal land to the internal/solder side

ground plane(s) should be used to help dissipation.

Copyright © 2013, Texas Instruments Incorporated

Submit Documentation Feedback

19

Product Folder Links: TPS51362